SOC Design Verification Engineer

Define and execute end-to-end verification strategy for multiple Testchips at Intel’s Hard IP division, from planning through signoff. Partner with architecture, design, structural design, and IP teams to make early technical calls, unblock cross-team issues, and deliver predictable high-quality verification collateral. Build reusable verification environments, tools, and complex testbenches while driving functional signoffs, coverage closure, and convergence of simulation and formal verification, including AI-assisted workflows.