Lead Software Engineer ( Verification )

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 5-8 yearsEducation: mastersSkills: ["Communication","Problem-solving","Team collaboration"]

Seeking a Lead Software Engineer to drive verification of complex architectures using UVM, SystemVerilog, and VHDL. You’ll develop verification libraries for IP/Sub-system/SoC, translate customer requirements into product enhancements, and collaborate across PV and field teams. Strong C/C++ background, excellent communication, and leadership to ramp up quickly on Cadence verification solutions in a Bengaluru team.

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Cadence Design Systems
Cadence Design Systems
5 months ago

Lead Software Engineer ( Verification )

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 16 hours agoStatus: Live

Job Summary

Seeking a Lead Software Engineer to drive verification of complex architectures using UVM, SystemVerilog, and VHDL. You’ll develop verification libraries for IP/Sub-system/SoC, translate customer requirements into product enhancements, and collaborate across PV and field teams. Strong C/C++ background, excellent communication, and leadership to ramp up quickly on Cadence verification solutions in a Bengaluru team.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Develop verification products based on customer requirements and architectures
  • •Analyze customer requirements and translate them to product enhancements with focus on verification of IP/Sub-system/SoC
  • •Provide active support and guidance to customer issues and escalate as needed
  • •Collaborate with PV, field and other teams to ensure verification solutions meet customer needs
  • •Lead and mentor junior engineers in verification methodologies and tool usage

Key Requirements

  • •B.Tech/B.E./M.Tech/ME in Electronics or related field
  • •Strong programming skills (OOP)
  • •Background in developing IP, Sub-system, SoC level verification environment with UVM and SW-driven (embedded C)
  • •UNIX shell scripting
  • •Strong knowledge of SystemVerilog/Verilog/VHDL and verification methodologies (UVM)
Experience:5-8 yearsSemiconductorEDAEmbedded
Education:Master's in Electronics
Skills:CommunicationProblem-solvingTeam collaboration
Tech Stack:SystemVerilogUVMVHDLVerilogEmbedded CUNIX shell scriptingAMBAPCIeUSBEthernet10 GigNVMeC++Python

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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