Cadence Design Systems

1 month ago

Principal Product Engineer – Digital & Signoff Group (DSG)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Bridge R&D, Applications Engineering, and customers to influence the next generation of chip design software for 7nm and below. Own place-and-route (P&R) resources, track and resolve issues for a robust release cycle, run competitive benchmarks for Power, Performance and Area, develop RTL-to-GDSII flows, and collaborate with Product Marketing to align capabilities with market roadmaps.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Key Responsibilities

•Serve as the primary place-and-route (P&R) resource for internal development teams and external customers.
•Collaborate with R&D to track, diagnose, and resolve software issues, ensuring a robust tool release cycle.
•Execute competitive benchmarks to demonstrate Cadence’s edge in Power, Performance, and Area (PPA).
•Develop and deploy customized RTL-to-GDSII methodologies and scripts to meet specific customer design goals.
•Partner with Product Marketing to align technical capabilities with market needs and customer roadmaps.

Key Requirements

•Bachelor's in Electronics Engineering plus 6+ years of industry experience OR Master's in Electronics Engineering plus 4+ years of digital implementation experience
•Deep understanding of the full ASIC design flow (RTL-to-GDSII) with a focus on physical design and timing analysis
•Proven hands-on experience with timing closure and PPA optimization at 7nm, 5nm, or below
•High familiarity with industry-standard EDA tools for synthesis, placement, routing, and signoff
•Proficiency in Tcl, Python, or Perl (AI-driven productivity tools a plus)

Experience:SemiconductorEDAASICChip design

Education:

Skills:CommunicationProblem-solvingTeam collaboration

Tech Stack:TclPythonPerlEDA toolsSynthesisPlacementRoutingSignoffRTLGDSIITiming analysis

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

Loading job details...

Preparing the role view and application actions.

Cadence Design Systems

1 month ago

Principal Product Engineer – Digital & Signoff Group (DSG)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Key Responsibilities

•Serve as the primary place-and-route (P&R) resource for internal development teams and external customers.
•Collaborate with R&D to track, diagnose, and resolve software issues, ensuring a robust tool release cycle.
•Execute competitive benchmarks to demonstrate Cadence’s edge in Power, Performance, and Area (PPA).
•Develop and deploy customized RTL-to-GDSII methodologies and scripts to meet specific customer design goals.
•Partner with Product Marketing to align technical capabilities with market needs and customer roadmaps.

Key Requirements

•Bachelor's in Electronics Engineering plus 6+ years of industry experience OR Master's in Electronics Engineering plus 4+ years of digital implementation experience
•Deep understanding of the full ASIC design flow (RTL-to-GDSII) with a focus on physical design and timing analysis
•Proven hands-on experience with timing closure and PPA optimization at 7nm, 5nm, or below
•High familiarity with industry-standard EDA tools for synthesis, placement, routing, and signoff
•Proficiency in Tcl, Python, or Perl (AI-driven productivity tools a plus)

Experience:SemiconductorEDAASICChip design

Education:

Skills:CommunicationProblem-solvingTeam collaboration

Tech Stack:TclPythonPerlEDA toolsSynthesisPlacementRoutingSignoffRTLGDSIITiming analysis

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor