Engineer IP Verification - Digital Design Verification
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 2-4 yearsSkills: ["Proactive","Debugging","Stakeholder communication","Risk communication","Collaboration"]Develop and execute block/chip RTL verification for DRAM designs by defining verification scope, building SV-UVM testbenches and test vectors, and running directed and constrained-random regressions. Analyze results, triage failures, improve functional/code coverage, and identify verification holes to support tapeout readiness. Debug RTL/testbench/environment issues, collaborate with international colleagues on verification flows, and communicate verification status and risks to stakeholders.
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