Sr Principal Design Engineer

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 154,000 - 286,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: mastersSkills: ["Debugging","Root-cause analysis","Analytical/problem-solving","Communication","Collaboration","Organizational planning","Emotional intelligence"]

Design, develop, verify, and productize system-level memory IP models for hardware-based verification platforms. Work across SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS—maintaining and improving existing models throughout their lifecycle. Apply strong RTL (Verilog/SystemVerilog) design, verification strategy, and debugging/root-cause analysis, while collaborating with internal and external customers and creating technical documentation.

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Cadence Design Systems
Cadence Design Systems
1 day ago

Sr Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 3 months ago

Job Summary

Design, develop, verify, and productize system-level memory IP models for hardware-based verification platforms. Work across SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS—maintaining and improving existing models throughout their lifecycle. Apply strong RTL (Verilog/SystemVerilog) design, verification strategy, and debugging/root-cause analysis, while collaborating with internal and external customers and creating technical documentation.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Design, develop, verify, and productize system-level memory IP models for hardware-based verification platforms.
  • •Develop memory models for LPDDR, HBM, NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS.
  • •Maintain, enhance, debug, and support existing memory IP products throughout their lifecycle.
  • •Develop high-quality RTL using Verilog/SystemVerilog and execute verification strategies using industry-standard simulation/emulation tools.
  • •Diagnose and resolve complex RTL, protocol, system, and customer issues; create and maintain technical documentation and work with internal/external customers on verification environments.

Pay and Benefits

Salary: USD 154,000 - 286,000 annually
Equity and Bonus:Equity
Perks:Paid Leave401kEquityHealth InsuranceDentalVision

Key Requirements

  • •MSEE or equivalent advanced degree with at least 5 years of experience designing complex protocols, RTL, and/or hardware systems.
  • •Extensive hands-on experience with Verilog/SystemVerilog RTL design.
  • •Strong understanding of RTL verification methodologies, tools, and flows.
  • •Proven ability to debug complex hardware, RTL, protocol, and system-level issues through root-cause analysis.
  • •Excellent written and verbal English communication, with the ability to work as an individual contributor while collaborating with engineering, product, and customer-facing teams.
Experience:5+ yearsHardware verificationSemiconductorMemory systems
Education:Master's
Skills:DebuggingRoot-cause analysisAnalytical/problem-solvingCommunicationCollaborationOrganizational planningEmotional intelligence
Languages:English
Tech Stack:VerilogSystemVerilogRTL designRTL verificationSimulationEmulationSDRAMLPDDRHBMNAND FlashONFIQSPIOSPIEMMCSD CardDFIUFSPerlTcl/TkC-shell

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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