Lead Analog SerDes Architect/Design Engineer

Intel
United States
Workplace: OnsiteFull timeUSD 220,920 - 311,890 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsEducation: mastersSkills: ["Collaboration","Design planning","Mentorship","Documentation","Guidance"]

Design and architect mixed-signal SerDes circuitry for Intel’s silicon photonics optical interconnects, targeting next-generation data center bandwidth growth. Define circuit architecture and performance tradeoffs, lead block-level development for analog CMOS/BiCMOS designs, and collaborate with digital designers. Plan designs against power, performance, schedule, and quality constraints, guide junior engineers, create test plans for post-silicon characterization, and produce detailed documentation through verification flows.

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Intel
Intel
7 months ago

Lead Analog SerDes Architect/Design Engineer

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Job Summary

Design and architect mixed-signal SerDes circuitry for Intel’s silicon photonics optical interconnects, targeting next-generation data center bandwidth growth. Define circuit architecture and performance tradeoffs, lead block-level development for analog CMOS/BiCMOS designs, and collaborate with digital designers. Plan designs against power, performance, schedule, and quality constraints, guide junior engineers, create test plans for post-silicon characterization, and produce detailed documentation through verification flows.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Define circuit architecture and enable designs meeting power and performance targets for next-generation optical interconnects based on system specifications.
  • •Lead block-level development of key integrated circuit components and collaborate with digital designers on mixed-signal integrated circuit design.
  • •Architect and design low voltage, low power mixed-signal integrated circuits for optical interconnect applications.
  • •Plan design work with constraints on performance, schedule, and quality, managing execution through design and verification cycles.
  • •Provide guidance to junior designers and layout engineers, develop test plans for post-silicon characterization, and document design work with review materials and detailed descriptions.

Pay and Benefits

Salary: USD 220,920 - 311,890 annually
Equity and Bonus:Equity
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies.
  • •Hands-on circuit design experience with SerDes blocks such as Equalizers, PLL, Phase-Interpolators, and CDR for 28Gbps+ data rates.
  • •Experience designing inductors, transmission lines, Trans-Impedance Amplifiers (TIA), and modulator drivers.
  • •Experience with precision analog circuits including ADC/DACs and with PAM4/NRZ links.
  • •Experience with mixed-signal design flow, full-chip designs, ESDs, and verification flows.
Experience:8+ yearsHigh-speed serial linksOptical communicationsAnalog CMOS/BiCMOSData center connectivity
Education:Master's in Electrical Engineering
Skills:CollaborationDesign planningMentorshipDocumentationGuidance
Tech Stack:SerDesEqualizersPLLPhase-InterpolatorsCDRInductorsTransmission lineTrans-Impedance Amplifiers (TIA)Modulator driversADCDACPAM4NRZMixed signal design flowESDsVerification flowsFull-chip designsOptical communications400G800G

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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