Distinguished Engineer, End-to-End Scaling Performance Architecture

Define long-term end-to-end performance architecture for accelerated computing systems, guiding how applications scale from single-processor to multi-die, multi-GPU, and multi-node platforms. Translate AI/HPC workload behavior into architectural requirements and measurable targets across DRAM, NVLink, and chip-to-chip interconnects. Evaluate system-level trade-offs, align domain teams on shared scaling strategy, recommend opportunities to shape product and technology decisions, and mentor performance architects.