ASIC VERIFICATION ENGINEER

Broadcom
India
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsSkills: ["Debugging","Coverage closure","Cross-functional collaboration","Test planning","Verification execution"]

Develop and maintain verification environments for Broadcom’s latest CSG switches, using a mix of SystemVerilog/SV-UVM. Own end-to-end verification by understanding specs and network/system topology, driving gate-level simulations, coverage closures, and end-to-end verification cycles. Partner with architecture/design teams to create test plans and close feature sets across blocks and top-level, including co-simulation debug for HW/SW flows.

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FursaFursa
Broadcom
Broadcom
2 days ago

ASIC VERIFICATION ENGINEER

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Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live

Job Summary

Develop and maintain verification environments for Broadcom’s latest CSG switches, using a mix of SystemVerilog/SV-UVM. Own end-to-end verification by understanding specs and network/system topology, driving gate-level simulations, coverage closures, and end-to-end verification cycles. Partner with architecture/design teams to create test plans and close feature sets across blocks and top-level, including co-simulation debug for HW/SW flows.
Location: India
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Develop and maintain verification environments for cutting-edge CSG switches using SV/UVM.
  • •Perform end-to-end verification by understanding specs and network/system topology and closing verification coverage.
  • •Collaborate with architecture/ uArch/ design teams to develop test plans and close feature sets across blocks and top-level.
  • •Run gate-level simulations and support end-to-end verification cycles, focusing on coverage closures.
  • •Own HW/SW co-simulation flows, performing debug and validation using simulation/formal tooling.

Key Requirements

  • •8+ years of verification experience with a strong chip/SoC background, supported by a Bachelor’s, Master’s, or PhD.
  • •Deep experience with chip-level (SoC) verification and SystemVerilog/UVM methodology.
  • •Experience with scripting in at least one of Perl, Python, or SED/Awk.
  • •Expertise in co-simulation (HW/SW) flows, debug, and understanding of end-to-end specs and network/system topology.
  • •Hands-on with coverage-driven methodology including GLS, coverage closures, gate-level simulations, and ATE; simulation tools like VCS/Verdi and formal tools like Jasper are required.
Experience:8+ yearsASIC verificationChip level (SoC) verificationUVMNetworkingFormal verification
Skills:DebuggingCoverage closureCross-functional collaborationTest planningVerification execution
Tech Stack:SystemVerilogSV/UVMUVMPerlPythonSED/AwkCo-SimulationHW/SWVCSVerdiJasperFormal toolsGLSCoverage Driven MethodologyATETest Bench AcceleratorsEmulation PlatformsPCIeEthernetAXI4.0

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn