Cadence Design Systems

1 month ago

Lead Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Lead design engineer responsible for Verilog RTL development and verification of data-path designs, ensuring timing closure and quality through RTL checks and simulations. Work with interface protocols such as UCIe, PCIe, USB, MIPI, and HDMI/Display, contributing to design reviews and mentoring teammates in a fast-paced hardware/EDA environment.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Design and implement Verilog RTL blocks and data-path for complex chips.
•Ensure timing closure and RTL quality through synthesis and constraints.
•Develop and run Verilog testbenches and simulations to verify designs.
•Collaborate on interfaces/protocols such as UCIe, PCIe, USB, MIPI (DPHY), HDMI/Display.
•Mentor junior engineers and participate in design reviews.

Key Requirements

•Proficient in Verilog coding and RTL design, data path designs.
•Knowledge of RTL checks ex- LINT, SDC, CDC
•Familiar with synthesis flow and timing constraints
•Experience in writing Verilog testbench and running simulations
•Familiar with interface protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display

Experience:SemiconductorHardwareEDA

Skills:VerilogRTLLINTSDCCDCSynthesisTimingVerilog testbenchSimulationUCIePCIeUSBMIPIHDMI

Tech Stack:VerilogRTLSynthesisTestbenchSimulationPCIeUSBMIPIHDMI

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

1 month ago

Lead Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Design and implement Verilog RTL blocks and data-path for complex chips.
•Ensure timing closure and RTL quality through synthesis and constraints.
•Develop and run Verilog testbenches and simulations to verify designs.
•Collaborate on interfaces/protocols such as UCIe, PCIe, USB, MIPI (DPHY), HDMI/Display.
•Mentor junior engineers and participate in design reviews.

Key Requirements

•Proficient in Verilog coding and RTL design, data path designs.
•Knowledge of RTL checks ex- LINT, SDC, CDC
•Familiar with synthesis flow and timing constraints
•Experience in writing Verilog testbench and running simulations
•Familiar with interface protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display

Experience:SemiconductorHardwareEDA

Skills:VerilogRTLLINTSDCCDCSynthesisTimingVerilog testbenchSimulationUCIePCIeUSBMIPIHDMI

Tech Stack:VerilogRTLSynthesisTestbenchSimulationPCIeUSBMIPIHDMI

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor