SerDes RTL Design Engineer

AMD
San Jose
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Problem-solving","Teamwork"]

Join AMD’s SerDes Technology team to design high-performance, multi-protocol wireline transceivers. You’ll perform RTL design in Verilog/SystemVerilog, collaborate with system link architects, apply low-power techniques, verify with block-level test benches, and work with cross-functional teams to bring advanced SerDes PHY designs from concept to silicon in US locations.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
AMD
AMD
4 months ago

SerDes RTL Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Join AMD’s SerDes Technology team to design high-performance, multi-protocol wireline transceivers. You’ll perform RTL design in Verilog/SystemVerilog, collaborate with system link architects, apply low-power techniques, verify with block-level test benches, and work with cross-functional teams to bring advanced SerDes PHY designs from concept to silicon in US locations.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Collaborate with system link architects to micro-architect cutting edge high-speed SerDes PHY design
  • •RTL design of digital blocks, such as calibration and adaptation loops, digital signal processing, clock-data-recovery
  • •Apply low power design techniques and perform PPA analysis
  • •Verify intended functionality with block-level test bench
  • •Run design checker tools such as LINT/CDC/RDC etc.

Key Requirements

  • •Bachelor's or master's degree in electrical engineering, computer engineering, or related field
  • •Proficient in logic design concepts and RTL coding using Verilog/System Verilog
  • •Experience in RTL design of digital blocks (calibration/adaptation loops, DSP, clock-data-recovery)
  • •Knowledge of synthesis flow and static timing analysis
  • •Experience with Python, Perl, TCL and/or other scripting language
Experience:SemiconductorsHardware
Education:Bachelor's
Skills:CommunicationProblem-solvingTeamwork
Languages:English
Tech Stack:VerilogSystemVerilogPythonPerlTCLSerDesPHYClock-data-recovery

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn