R&D Engineer IC Design
San Jose
Workplace: OnsiteFull time120,000 - 192,000Function: Design (Product/UX/UI/Visual)Experience: 6+ yearsEducation: mastersSkills: ["SystemVerilog","UVM","Verification","Testbenches","C","RTL","Gatesim"]Verify complex switch designs through SystemVerilog-based environments, building testbenches and transactors, and executing test plans for RTL and gatesim verifications at block and chip levels. Develop ATE testing vectors and C-based diagnostics for silicon, with emphasis on UVM methodology and verification tooling within a hardware/semiconductor context.

