Senior Principal Hardware Engineer

Cadence Design Systems
United States
Workplace: OnsiteFull timeUSD 136,500 - 253,500 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 5-15 yearsEducation: high_schoolSkills: ["Communication","Problem-solving","Collaboration","Self-motivated","Cross-functional teamwork"]

Drive physical design solutions for complex chips from synthesis through tape-out, covering floorplanning, clock construction, placement/routing, and signoff closure (timing analysis, physical verification, IR/EM). Collaborate with RTL, DFT, and architecture teams, and work with R&D to improve tools and flows to boost design quality and execution. Optimize power/performance/area for advanced process nodes and close designs to timing, power, IR/EM, and foundry specifications.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
1 month ago

Senior Principal Hardware Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Drive physical design solutions for complex chips from synthesis through tape-out, covering floorplanning, clock construction, placement/routing, and signoff closure (timing analysis, physical verification, IR/EM). Collaborate with RTL, DFT, and architecture teams, and work with R&D to improve tools and flows to boost design quality and execution. Optimize power/performance/area for advanced process nodes and close designs to timing, power, IR/EM, and foundry specifications.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Drive logic synthesis, floorplan, place and route (PNR), and clock construction solutions.
  • •Continuously improve existing tools, flows, and methodologies.
  • •Optimize power, performance, and area to meet design requirements.
  • •Collaborate closely with cross-functional teams to ensure proper design execution.
  • •Close designs to timing, power, IR/EM, and foundry specifications and support R&D tool/flow improvements.

Pay and Benefits

Salary: USD 136,500 - 253,500 annually
Perks:Paid LeavePaid Holidays401kHealth InsuranceEquity

Key Requirements

  • •BS with 10+ years, MS with 7+ years, or PhD with 5+ years, or 8–15+ years hands-on physical design experience.
  • •Successfully owned and driven blocks/SoCs to tape-out.
  • •Comfortable working with advanced process nodes and technologies.
  • •Experience with at least one scripting language such as PERL, Python, TCL, or Shell (preferred).
  • •Strong written/verbal communication and problem-solving to collaborate with teams and deliver results.
Experience:5-15 yearsHardware emulation-accelerationPhysical designSoC design
Education:High School
Skills:CommunicationProblem-solvingCollaborationSelf-motivatedCross-functional teamwork
Tech Stack:PERLPythonTCLShell

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor