Arista Networks

2 weeks ago

Senior Signal Integrity / Power Integrity (SI/PI) Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 2 hours agoStatus: Live

Job Summary

Design, simulate, and characterize high-speed interconnects for next-generation SerDes used in Ethernet and optical networking. Use 3D EM solvers (Ansys HFSS, SiWave, Cadence Sigrity) and SI/PI measurement techniques (VNA, TDR, BERT) to extract and validate channel performance. Collaborate with hardware, mechanical, and packaging teams on routing, stack-up, and power delivery, and support bring-up/debug of production boards.

Location: Santa Clara

Workplace: Onsite

Employment Type: Full time

Job Function: Energy & Utilities Operations

Seniority: Mid level

Key Responsibilities

•Perform 3D EM design and simulation of high-speed interconnects (channels, vias, packages, connectors) for 112G/224G PAM4 SerDes.
•Develop and validate test vehicles to characterize next-generation PCB materials, packages, and interconnects.
•Conduct S-parameter and time-domain measurements (VNA, TDR, BERT) to extract channel performance and validate modeling correlation.
•Perform link-level analysis for advanced standards (Ethernet 800G/1.6T, PCIe Gen6/Gen7, CXL) using Keysight ADS or Cadence SystemSI.
•Collaborate with hardware, mechanical, and packaging teams to optimize stack-up, breakout, and routing strategies, and support bring-up/debug of production boards.

Pay and Benefits

Salary: USD 162,000 - 225,000 annually

Equity and Bonus:Equity

Perks:Health InsuranceDentalVisionWellness StipendIncome ProtectionTax Savings

Key Requirements

•BS/MS/PhD in Electrical Engineering, Physics, or related field with focus on electromagnetics, signal integrity, or high-speed digital design.
•Solid understanding of signal integrity theory, S-parameter analysis, and channel modeling.
•Hands-on experience with 2.5D/3D EM solvers such as Ansys HFSS, SiWave, Sigrity, and CST.
•Strong lab skills using oscilloscopes, VNAs, TDRs, BERTs, and Ethernet compliance tools.
•Familiarity with advanced PCB materials (e.g., Megtron 7, Tachyon 100G, SLP) and experience analyzing and simulating 56G/112G/224G PAM4 and NRZ serial links.

Education:

Skills:CommunicationCollaboration

Languages:English

Tech Stack:Ansys HFSSSiWaveCadence SigrityCSTVNATDRBERTKeysight ADSCadence SystemSIS-parameter analysisOscilloscopesMegtron 7Tachyon 100GSLPEMI/EMC

Company Brief

Arista Networks

Designs and sells high-performance cloud networking hardware and software for large-scale data centers and enterprise environments, including switches, routers, and network operating systems focused on programmability, telemetry, and low-latency networking.

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 2004

Glassdoor: 4.1

Website LinkedIn

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Arista Networks

2 weeks ago

Senior Signal Integrity / Power Integrity (SI/PI) Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 2 hours agoStatus: Live

Job Summary

Location: Santa Clara

Workplace: Onsite

Employment Type: Full time

Job Function: Energy & Utilities Operations

Seniority: Mid level

Key Responsibilities

•Perform 3D EM design and simulation of high-speed interconnects (channels, vias, packages, connectors) for 112G/224G PAM4 SerDes.
•Develop and validate test vehicles to characterize next-generation PCB materials, packages, and interconnects.
•Conduct S-parameter and time-domain measurements (VNA, TDR, BERT) to extract channel performance and validate modeling correlation.
•Perform link-level analysis for advanced standards (Ethernet 800G/1.6T, PCIe Gen6/Gen7, CXL) using Keysight ADS or Cadence SystemSI.
•Collaborate with hardware, mechanical, and packaging teams to optimize stack-up, breakout, and routing strategies, and support bring-up/debug of production boards.

Pay and Benefits

Salary: USD 162,000 - 225,000 annually

Equity and Bonus:Equity

Perks:Health InsuranceDentalVisionWellness StipendIncome ProtectionTax Savings

Key Requirements

•BS/MS/PhD in Electrical Engineering, Physics, or related field with focus on electromagnetics, signal integrity, or high-speed digital design.
•Solid understanding of signal integrity theory, S-parameter analysis, and channel modeling.
•Hands-on experience with 2.5D/3D EM solvers such as Ansys HFSS, SiWave, Sigrity, and CST.
•Strong lab skills using oscilloscopes, VNAs, TDRs, BERTs, and Ethernet compliance tools.
•Familiarity with advanced PCB materials (e.g., Megtron 7, Tachyon 100G, SLP) and experience analyzing and simulating 56G/112G/224G PAM4 and NRZ serial links.

Education:

Skills:CommunicationCollaboration

Languages:English

Tech Stack:Ansys HFSSSiWaveCadence SigrityCSTVNATDRBERTKeysight ADSCadence SystemSIS-parameter analysisOscilloscopesMegtron 7Tachyon 100GSLPEMI/EMC

Company Brief

Arista Networks

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 2004

Glassdoor: 4.1

Website LinkedIn