Physical Design Methodology Staff Engineer

AMD
Austin
Workplace: OnsiteFull timeUSD 126,700 - 217,200 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: []

Own the optimization of physical design methodologies for CPU cores, focusing on the “how” behind EDA tool flows and aggressive PPA targets. Design end-to-end physical implementation flows from synthesis through signoff, build automated signoff loops (STA, IR/EM, physical verification), and develop Tcl/Python frameworks for design space exploration, ECO implementation, and multi-corner timing closure. Drive EDA vendor collaboration and data-driven methodology improvements to reduce turnaround time and improve predictability.

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FursaFursa
AMD
AMD
2 days ago

Physical Design Methodology Staff Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 18 hours agoStatus: Live

Job Summary

Own the optimization of physical design methodologies for CPU cores, focusing on the “how” behind EDA tool flows and aggressive PPA targets. Design end-to-end physical implementation flows from synthesis through signoff, build automated signoff loops (STA, IR/EM, physical verification), and develop Tcl/Python frameworks for design space exploration, ECO implementation, and multi-corner timing closure. Drive EDA vendor collaboration and data-driven methodology improvements to reduce turnaround time and improve predictability.
Location: Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Design, implement, and maintain end-to-end physical implementation flows (synthesis through signoff) with scalability, reproducibility, and high QoR.
  • •Optimize EDA toolchains by driving vendor adoption, evaluating new features, and troubleshooting complex tool behavior.
  • •Develop and deploy scripting frameworks (Tcl/Python) to automate design space exploration, ECO implementation, and multi-corner timing closure.
  • •Analyze and tune PPA-related tool settings (placement density, routing congestion management, CTS strategies) to meet aggressive frequency and power targets.
  • •Build and refine automated signoff loops (STA, IR/EM, physical verification) and manage constraint engineering (SDC, MMMC) to support tape-outs with minimal iterations.

Pay and Benefits

Salary: USD 126,700 - 217,200 annually

Key Requirements

  • •Expert-level proficiency with physical design platforms (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus).
  • •Advanced Tcl/Python/Perl skills to automate design space exploration, ECO implementation, and multi-corner timing closure.
  • •Deep understanding of advanced-node physical effects (7nm/5nm/3nm) and configuring EDA tools to mitigate parasitic, crosstalk, and LDE issues.
  • •Mastery of signoff methodology and ecosystem (e.g., PrimeTime SI, RedHawk-SC, Voltus, Calibre) with experience building push-button signoff flows.
  • •Ability to develop and validate complex SDC constraints and manage MMMC environments with high-frequency CPU timing exceptions.
Experience:EDASemiconductorsCPUHigh-performance computing
Education:Master's in Electrical Engineering or Computer Engineering
Languages:English
Tech Stack:TclPythonPerlSynopsys Fusion CompilerICC2Cadence InnovusPrimeTime SIRedHawk-SCVoltusCalibreUPFCPFMMMCSDCSTAIR/EMPhysical VerificationCTSECOMulti-corner timing closure

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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