IOMMU Verification Engineer

AMD
Vancouver, Markham
Workplace: HybridFull timeFunction: QA, Test & Release EngineeringEducation: mastersSkills: ["Analytical thinking","Problem-solving","Attention to detail","Teamwork","Communication"]

Join the IOHUB/NBIO team to verify complex ASIC IP for I/O connectivity and virtualization technologies used in data center and machine learning workloads. You’ll help define verification architecture and test plans, build and maintain verification environments and VIP/libraries, run regressions with coverage closure, and debug issues found in post-silicon using dynamic simulation and/or formal verification. You’ll also perform code reviews and develop scripts/tools to improve verification execution and methodology.

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FursaFursa
AMD
AMD
6 days ago

IOMMU Verification Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live

Job Summary

Join the IOHUB/NBIO team to verify complex ASIC IP for I/O connectivity and virtualization technologies used in data center and machine learning workloads. You’ll help define verification architecture and test plans, build and maintain verification environments and VIP/libraries, run regressions with coverage closure, and debug issues found in post-silicon using dynamic simulation and/or formal verification. You’ll also perform code reviews and develop scripts/tools to improve verification execution and methodology.
Location: Vancouver, Markham
Workplace: Hybrid
Employment Type: Full time
Job Function: QA, Test & Release Engineering

Key Responsibilities

  • •Collaborate with IP architects to create verification architecture and development plans.
  • •Own end-to-end verification of key features for complex IP blocks.
  • •Develop and maintain test plans, verification environments, regressions, and coverage closure.
  • •Build/maintain VIP, libraries, verification environments, and testcases (random and directed) using System Verilog/SVA/UVM.
  • •Triaging/debugging regressions, analyzing code and functional coverage, reproducing post-silicon bugs in simulation/formal verification, and participating in code reviews.

Key Requirements

  • •Strong ASIC verification experience is required.
  • •Strong understanding of digital design and computer architecture.
  • •Proficiency in Verilog, SystemVerilog, SVA, C/C++, UVM, OOP, and working in Linux and Windows environments.
  • •Ability to debug SystemVerilog RTL code using simulation tools.
  • •BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science.
Experience:ASIC verificationDigital designComputer architecturePost-siliconFormal verification
Education:Master's
Skills:Analytical thinkingProblem-solvingAttention to detailTeamworkCommunication
Languages:En-us
Tech Stack:VerilogSystemVerilogSystem VerilogSVAUVMC/C++LinuxWindowsFormal verificationSimulation tools

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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