Principal, SMTS, DRAM Systems Architect

Micron Technology
Boise, Idaho
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 10+ yearsEducation: mastersSkills: ["Communication","Mentoring","Coaching","Multi-tasking","Problem-solving"]

Architect, design, develop, optimize, verify, and support high-speed IO and clocking circuits for Micron’s DRAM IP design team. Own equalization and bandwidth-extension efforts, analyze IO impairments (including clock jitter and duty cycle distortion) and their impact on DRAM system timing, and create modeling/simulation methods for circuit-to-system metrics. Partner with product engineering and SI teams for silicon-to-simulation correlation, and collaborate with process integration teams on next-generation process nodes.

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Micron Technology
Micron Technology
2 weeks ago

Principal, SMTS, DRAM Systems Architect

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Job Summary

Architect, design, develop, optimize, verify, and support high-speed IO and clocking circuits for Micron’s DRAM IP design team. Own equalization and bandwidth-extension efforts, analyze IO impairments (including clock jitter and duty cycle distortion) and their impact on DRAM system timing, and create modeling/simulation methods for circuit-to-system metrics. Partner with product engineering and SI teams for silicon-to-simulation correlation, and collaborate with process integration teams on next-generation process nodes.
Location: Boise, Idaho
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Mid level

Key Responsibilities

  • •Define, innovate, design, optimize, and verify high-speed IO and clocking circuits used in new DRAM products.
  • •Apply high-speed circuit design techniques and improve performance evaluation for timing and jitter sensitivity at circuit and full-chip levels.
  • •Develop accurate modeling, analysis, and simulation methodology to capture circuit performance metrics and their impact to product specifications.
  • •Collaborate with Product Engineering and SI teams to compare silicon performance with simulation results and support correlation activities.
  • •Work with process integration and transistor modeling teams on Micron’s next process node.

Pay and Benefits

Perks:Health InsuranceDentalVisionParental LeavePaid LeavePaid Holidays

Key Requirements

  • •Minimum MSEE + 10 years or BSEE + 12 years designing high-speed IO interface, timing, and clocking circuits with proven silicon success.
  • •Ability to supervise layout work and apply good layout practices for high-speed circuits to minimize parasitic impacts.
  • •Strong communication skills to convey sophisticated technical concepts verbally and in writing.
  • •Mentoring and coaching engineers early in their careers.
  • •Experience with DRAM circuit design and/or channel modeling and characterization, transceiver noise/timing budget analysis, equalization techniques, and SI knowledge is preferred.
Experience:10+ yearsDRAMSemiconductorHigh-speed IOTiming and clockingSilicon validation
Education:Master's in Electrical Engineering
Skills:CommunicationMentoringCoachingMulti-taskingProblem-solving
Tech Stack:PERLPythonAI/MLCMOS

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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