[Closed] Senior Manager of Board Design at Neurophos (San Jose, Austin)

This position is no longer accepting applications.

Neurophos

1 month ago

Senior Manager of Board Design

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 9 minutes agoStatus: Closed

Job Summary

Lead end-to-end PCB development and integration for high-speed, optoelectronic board systems in a senior technical leadership role. Oversee architecture, bring-up, verification, and production release across both conventional hardware boards and optoelectronics interfaces, collaborating with cross-functional teams to meet stringent signal integrity, power, and thermal requirements in a cutting-edge AI hardware platform.

Location: San Jose, Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Own end-to-end PCB development for all OPU product boards, including host interface carrier boards, silicon photonic IC interposers, metasurface/SLM driver boards, and subsystem evaluation platforms.
•Define board architecture, layer stack-ups, and design rules for high-speed digital interfaces (PCIe Gen 5, UCIe, DDR5) and high-fidelity analog/optoelectronic drive circuits on the same or adjacent boards.
•Lead schematic capture and layout reviews, enforcing DFM, DFT, and signal integrity standards across both digital and optoelectronic board domains.
•Drive board-level bring-up, debug, and characterization for complex mixed-signal systems; establish repeatable verification methodologies covering both electrical and optical functional tests.
•Maintain schematic block libraries, footprint libraries, and simulation models that span digital, analog, and optoelectronic component families.

Pay and Benefits

Equity and Bonus:Equity

Perks:Health InsurancePaid Leave401kEquityDentalVisionHsa

Key Requirements

•Bachelor’s or Master’s degree in electrical engineering or a closely related discipline.
•10+ years of hands-on PCB and hardware engineering experience, with at least 3 years in a people management or technical lead role.
•Deep expertise in high-speed digital PCB design for SerDes rates of 25G and above (PCIe Gen 4/5, 56G/112G SerDes).
•Hands-on experience with optoelectronic board design: laser driver ICs, TIA circuits, high-speed DAC/ADC interfaces, or silicon photonics IC integration at the board level.
•Proficiency with industry-standard EDA toolchains (Cadence Allegro/OrCAD, Altium, or equivalent) and SI/PI simulation tools (HyperLynx, Sigrity, or equivalent).

Experience:PhotonicAI hardwareOptoelectronicsHardware startup

Education:Bachelor's

Skills:LeadershipTeam managementCommunicationProblem-solvingMentorship

Languages:English

Tech Stack:PCIe Gen5UCIeDDR5Cadence AllegroOrCADAltiumHyperLynxSigrityPDN designVRM

Company Brief

Neurophos

Develops metamaterial-based photonic optical processing units (OPUs) to deliver high-performance, energy-efficient AI inference chips for datacenters, aiming to scale photonic compute to exaflop levels.

Industry: Deep Tech

Company Size: Small (11 to 50 employees)

Growth: Growth Stage Startup

Funding: Series A

Headquarters: Austin, United States

Founded: 2020

Website LinkedIn

Loading job details...

Preparing the role view and application actions.

This position is no longer accepting applications.

Neurophos

1 month ago

Senior Manager of Board Design

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 9 minutes agoStatus: Closed

Job Summary

Location: San Jose, Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Own end-to-end PCB development for all OPU product boards, including host interface carrier boards, silicon photonic IC interposers, metasurface/SLM driver boards, and subsystem evaluation platforms.
•Define board architecture, layer stack-ups, and design rules for high-speed digital interfaces (PCIe Gen 5, UCIe, DDR5) and high-fidelity analog/optoelectronic drive circuits on the same or adjacent boards.
•Lead schematic capture and layout reviews, enforcing DFM, DFT, and signal integrity standards across both digital and optoelectronic board domains.
•Drive board-level bring-up, debug, and characterization for complex mixed-signal systems; establish repeatable verification methodologies covering both electrical and optical functional tests.
•Maintain schematic block libraries, footprint libraries, and simulation models that span digital, analog, and optoelectronic component families.

Pay and Benefits

Equity and Bonus:Equity

Perks:Health InsurancePaid Leave401kEquityDentalVisionHsa

Key Requirements

•Bachelor’s or Master’s degree in electrical engineering or a closely related discipline.
•10+ years of hands-on PCB and hardware engineering experience, with at least 3 years in a people management or technical lead role.
•Deep expertise in high-speed digital PCB design for SerDes rates of 25G and above (PCIe Gen 4/5, 56G/112G SerDes).
•Hands-on experience with optoelectronic board design: laser driver ICs, TIA circuits, high-speed DAC/ADC interfaces, or silicon photonics IC integration at the board level.
•Proficiency with industry-standard EDA toolchains (Cadence Allegro/OrCAD, Altium, or equivalent) and SI/PI simulation tools (HyperLynx, Sigrity, or equivalent).

Experience:PhotonicAI hardwareOptoelectronicsHardware startup

Education:Bachelor's

Skills:LeadershipTeam managementCommunicationProblem-solvingMentorship

Languages:English

Tech Stack:PCIe Gen5UCIeDDR5Cadence AllegroOrCADAltiumHyperLynxSigrityPDN designVRM

Company Brief

Neurophos

Industry: Deep Tech

Company Size: Small (11 to 50 employees)

Growth: Growth Stage Startup

Funding: Series A

Headquarters: Austin, United States

Founded: 2020

Website LinkedIn