Lead Digital Verification Engineer

Cadence Design Systems
Montreal, Ottawa, Toronto
Workplace: OnsiteFull timeCAD 89,600 - 166,400 annuallyFunction: Administration & Executive AssistanceEducation: bachelorsSkills: ["Independent work","Communication","Problem-solving","Collaboration","Self-starter"]

Develop and verify high-performance digital IP for industry-standard protocols by owning RTL verification and building reusable verification components and environments. Contribute across the verification lifecycle, including flow development, verification/test plan creation, stimulus generation, and coverage and code coverage closure. Collaborate with digital and analog design teams and other stakeholders while demonstrating strong logic fundamentals and problem-solving and communication skills.

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Cadence Design Systems
Cadence Design Systems
2 days ago

Lead Digital Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 52 minutes agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Develop and verify high-performance digital IP for industry-standard protocols by owning RTL verification and building reusable verification components and environments. Contribute across the verification lifecycle, including flow development, verification/test plan creation, stimulus generation, and coverage and code coverage closure. Collaborate with digital and analog design teams and other stakeholders while demonstrating strong logic fundamentals and problem-solving and communication skills.
Location: Montreal, Ottawa, Toronto
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Verify digital RTL modules and develop reusable verification components and environments.
  • •Own the verification lifecycle including flow development, test plan development, and execution.
  • •Drive functional coverage closure and code coverage closure.
  • •Create stimuli and analyze coverage to support end-to-end verification progress updates.
  • •Collaborate with design teams, verification teams, and project management across multiple geographies.
Travel: Low travel

Pay and Benefits

Salary: CAD 89,600 - 166,400 annually
Equity and Bonus:Equity
Perks:Paid LeavePaid HolidaysRrspTfsaDentalVisionEap BenefitsLife InsuranceDisabilityTravel AllowanceLifestyle Spending

Key Requirements

  • •Bachelor of Science in Electrical/Computer Engineering or Computer Science.
  • •Understanding of verification architecture and methodologies, including metric-driven verification and universal verification methodologies.
  • •Experience creating and planning functional coverage and checks.
  • •Understanding of SystemVerilog Assertions (SVAs) and digital design flow.
  • •Be able to work independently and communicate effectively with technical staff.
Experience:Digital verificationPhysical IPProtocolsFormal verificationMixed-signal design
Education:Bachelor's in Electrical (EE)/Computer Engineering (CPE) or Computer Science (CSC)
Skills:Independent workCommunicationProblem-solvingCollaborationSelf-starter
Languages:EnglishFrench
Tech Stack:RTLSystemVerilogUVMSystemVerilog AssertionsSVAsPythonPerlRubySedAwkCPFUPFPCIeUSBSATAEthernetDisplay PortHDMI

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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