Custom SOC IP Verification Engineer

NVIDIA
United States
Full timeUSD 136,000 - 218,500 annuallyFunction: QA, Test & Release EngineeringExperience: 5+ yearsEducation: bachelorsSkills: ["Verification","Collaboration","Test planning","Cross-functional coordination","Performance analysis"]

Verify next-generation custom SoC and IP by driving ASIC verification for fabric and interconnect subsystems, from IP bring-up through full chip integration. Own correctness, performance, and compliance checks across DMA, routing, arbitration, ordering, flow control, and protocol compliance. Build UVM-based UVM/SystemVerilog test plans and constrained-random/direct testbenches, and collaborate closely with architecture, SW/FW, design, modeling, emulation, and post-silicon teams.

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FursaFursa
NVIDIA
NVIDIA
4 days ago

Custom SOC IP Verification Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 20 hours agoStatus: Live

Job Summary

Verify next-generation custom SoC and IP by driving ASIC verification for fabric and interconnect subsystems, from IP bring-up through full chip integration. Own correctness, performance, and compliance checks across DMA, routing, arbitration, ordering, flow control, and protocol compliance. Build UVM-based UVM/SystemVerilog test plans and constrained-random/direct testbenches, and collaborate closely with architecture, SW/FW, design, modeling, emulation, and post-silicon teams.
Location: United States
Employment Type: Full time
Job Function: QA, Test & Release Engineering
Seniority: Mid level

Key Responsibilities

  • •Conduct ASIC design verification for fabric and interconnect IP blocks and full chip integration, including DMA, routing, arbitration, ordering, flow control, and protocol compliance.
  • •Develop and implement UVM-based test plans for fabric and interconnect verification across IP-level and system-level scenarios.
  • •Design and implement constrained-random and directed SystemVerilog testbenches for interconnect fabrics, NoC topologies, and multi-agent SoC integrations.
  • •Collaborate with architecture, SW/FW, design, modeling, emulation, and post-silicon validation teams to ensure first-time right verification plans and execution.
  • •Drive development of silicon and platform verification strategies and methodologies for fabric and interconnect subsystems.

Pay and Benefits

Salary: USD 136,000 - 218,500 annually
Equity and Bonus:Equity

Key Requirements

  • •B.S. or M.S. in Computer Engineering, Electrical Engineering, or related field (or equivalent experience).
  • •5+ years of experience in ASIC verification focused on fabric, interconnect, or network-on-chip (NoC) verification at both IP and full chip levels.
  • •Strong knowledge of SystemVerilog and UVM methodology.
  • •Hands-on experience with interconnect and bus protocols such as AMBA AXI or CHI, including ordering, coherency, and flow control semantics.
  • •Proficiency in scripting languages including Python, Perl, or TCL.
Experience:5+ yearsASIC verificationSoCIP integrationNetwork-on-chipInterconnect protocolsUVMSystemVerilog
Education:Bachelor's in Computer Engineering, Electrical Engineering, or related field
Skills:VerificationCollaborationTest planningCross-functional coordinationPerformance analysis
Tech Stack:SystemVerilogUVMPythonPerlTCLAMBA AXICHIUVM-based environmentsConstrained-randomDirected testbenchesDMARoutingArbitrationOrderingFlow controlSystemVerilog testbenchesSVAFormal verificationPalladiumVeloce

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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Glassdoor: 4.3
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