Neurophos

1 month ago

Staff Analog Layout Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Seasoned analog layout engineer for high-speed RF/analog ICs, delivering IP-level floor planning, power distribution, and layout optimization for deep-submicron processes. Collaborates with circuit designers and EDA vendors to ensure fit into production flow, tackling DFM constraints, EM/IR, and tight signal integrity for photonics-enabled AI hardware.

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Perform custom IC layout execution of high-speed analog/RF circuits.
•Optimize layout solutions to meet stringent TSMC manufacturing constraints, DFM rules, and antenna restrictions
•Deliver IP-level floor planning, power planning, and signal distribution, implementing layout techniques for strict ESD and Latch-up prevention.
•Execute and debug block-level design sign-offs, including DRC, LVS, and RC Extraction using standard industry tools.
•Evaluate layout trade-offs among area, yield, and performance; implement the power and clock delivery networks to ensure power and signal integrity.

Pay and Benefits

Perks:Health InsurancePaid LeaveEquityDentalVisionLife Insurance

Key Requirements

•B.S. or M.S. in Electrical Engineering, Computer Engineering, or a closely related discipline.

Experience:3-8 yearsSemiconductorHardwareIC layoutPhotonic

Education:Bachelor's

Skills:Cadence VirtuosoSynopsys Custom CompilerMentor CalibreSiemens ICVEDA toolsLayout techniquesElectro-migrationEM/IRParasitic reductionMatching strategiesTCLPythonPerl

Tech Stack:Cadence VirtuosoSynopsys Custom CompilerMentor CalibreSiemens ICVTCLPerlPythonEM/IRParasitic reduction

Company Brief

Neurophos

Develops metamaterial-based photonic optical processing units (OPUs) to deliver high-performance, energy-efficient AI inference chips for datacenters, aiming to scale photonic compute to exaflop levels.

Industry: Deep Tech

Company Size: Small (11 to 50 employees)

Growth: Growth Stage Startup

Funding: Series A

Headquarters: Austin, United States

Founded: 2020

Website LinkedIn

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Neurophos

1 month ago

Staff Analog Layout Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Perform custom IC layout execution of high-speed analog/RF circuits.
•Optimize layout solutions to meet stringent TSMC manufacturing constraints, DFM rules, and antenna restrictions
•Deliver IP-level floor planning, power planning, and signal distribution, implementing layout techniques for strict ESD and Latch-up prevention.
•Execute and debug block-level design sign-offs, including DRC, LVS, and RC Extraction using standard industry tools.
•Evaluate layout trade-offs among area, yield, and performance; implement the power and clock delivery networks to ensure power and signal integrity.

Pay and Benefits

Perks:Health InsurancePaid LeaveEquityDentalVisionLife Insurance

Key Requirements

•B.S. or M.S. in Electrical Engineering, Computer Engineering, or a closely related discipline.

Experience:3-8 yearsSemiconductorHardwareIC layoutPhotonic

Education:Bachelor's

Skills:Cadence VirtuosoSynopsys Custom CompilerMentor CalibreSiemens ICVEDA toolsLayout techniquesElectro-migrationEM/IRParasitic reductionMatching strategiesTCLPythonPerl

Tech Stack:Cadence VirtuosoSynopsys Custom CompilerMentor CalibreSiemens ICVTCLPerlPythonEM/IRParasitic reduction

Company Brief

Neurophos

Industry: Deep Tech

Company Size: Small (11 to 50 employees)

Growth: Growth Stage Startup

Funding: Series A

Headquarters: Austin, United States

Founded: 2020

Website LinkedIn