Cadence Design Systems

3 months ago

Lead Customer Engagement Engineer- Liberate

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Lead the adoption and integration of Cadence Liberate characterization for signoff-quality libraries, collaborating with Foundry PDK and Design Service teams to deliver standard cell, IO, and memory libraries and ensure library models align with signoff and downstream STA, power, and reliability analysis.

Location: Shanghai

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Key Responsibilities

•Support foundry PDK teams in development, validation, and maintenance of Liberate characterization techfiles for standard cell, IO, and memory libraries.
•Collaborate with foundry teams to define SPICE corner, PVT, and RC assumptions used for library signoff.
•Enable generation of signoff-quality Liberty models (NLDM / CCS / CCSP) aligned with foundry requirements.
•Support characterization of timing, power, leakage, noise, and SI effects for advanced nodes.
•Assist foundry PDK qualification and IP vendor enablement through library quality checks and debugging.

Key Requirements

•Experience with Cadence Liberate Characterization Suite and deploying signoff-quality libraries (standard cell, IO, memory).
•Knowledge of library modeling methodology, techfile development, and design-ready reference flows aligned with foundry signoff requirements.
•Ability to define SPICE corner, PVT, and RC assumptions for library signoff in collaboration with foundry teams.
•Experience generating signoff-quality Liberty models (NLDM/CCS/CCSP) and validating timing, power, leakage, noise, and SI effects for advanced nodes.
•Experience debugging library quality issues and ensuring consistency between library models and downstream STA, power, and reliability analyses.

Experience:SemiconductorsEDASoC

Skills:Liberty modelsTimingPowerSignal integrityEDASoC

Tech Stack:Cadence LiberateLiberate Characterization SuiteNLDMCCSCCSPSPICEPVTRCLIBERTY

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

3 months ago

Lead Customer Engagement Engineer- Liberate

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Shanghai

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Key Responsibilities

•Support foundry PDK teams in development, validation, and maintenance of Liberate characterization techfiles for standard cell, IO, and memory libraries.
•Collaborate with foundry teams to define SPICE corner, PVT, and RC assumptions used for library signoff.
•Enable generation of signoff-quality Liberty models (NLDM / CCS / CCSP) aligned with foundry requirements.
•Support characterization of timing, power, leakage, noise, and SI effects for advanced nodes.
•Assist foundry PDK qualification and IP vendor enablement through library quality checks and debugging.

Key Requirements

•Experience with Cadence Liberate Characterization Suite and deploying signoff-quality libraries (standard cell, IO, memory).
•Knowledge of library modeling methodology, techfile development, and design-ready reference flows aligned with foundry signoff requirements.
•Ability to define SPICE corner, PVT, and RC assumptions for library signoff in collaboration with foundry teams.
•Experience generating signoff-quality Liberty models (NLDM/CCS/CCSP) and validating timing, power, leakage, noise, and SI effects for advanced nodes.
•Experience debugging library quality issues and ensuring consistency between library models and downstream STA, power, and reliability analyses.

Experience:SemiconductorsEDASoC

Skills:Liberty modelsTimingPowerSignal integrityEDASoC

Tech Stack:Cadence LiberateLiberate Characterization SuiteNLDMCCSCCSPSPICEPVTRCLIBERTY

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor