Etched

1 month ago

Formal Verification - DV

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 5 hours agoStatus: Live

Job Summary

Seeking a Formal Verification Engineer to drive verification across ASIC DV teams for complex IP blocks, interfaces, and SoC integration. Collaborate with architects, RTL designers, DV engineers, emulation and software teams to prove design correctness, uncover corner-case bugs, and improve verification closure across the full chip using SystemVerilog, formal methods, and industry-standard tools.

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Software Engineering

Key Responsibilities

•Define and drive formal verification strategy across the ASIC DV team for complex IP blocks, interface subsystems, and SoC integration logic.
•Develop formal verification plans covering functional correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom.
•Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models.
•Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics to establish formal sign-off confidence.
•Work with architects and RTL designers to translate design intent and specifications into high-value formal properties and closure criteria.

Pay and Benefits

Perks:MedicalDentalVisionHousing SubsidyRelocationMeal Allowance

Key Requirements

•5+ years of design verification experience with significant hands-on formal verification on complex digital designs or shipping silicon.
•Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology.
•Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.
•Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces.
•Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models.

Experience:5+ yearsSemiconductorsASICHardware

Skills:SystemVerilogSystemVerilog AssertionsUVM DVVerilogPCIeEthernetNoCsDMASoC

Languages:English

Tech Stack:SystemVerilogSystemVerilog AssertionsCadence JasperGoldSynopsys VC FormalSiemens Questa FormalUVMVerilogPCIeEthernetNoCsDMA

Company Brief

Etched

Designs transformer‑specialized AI inference ASICs (product: Sohu) to accelerate large‑language‑model workloads, working with TSMC for fabrication and targeting energy‑efficient inference performance.

Industry: Hardware Devices

Company Size: Medium (51 to 250 employees)

Growth: Early Stage Startup

Valuation: Unicorn (USD 1B+)

Funding: Series A

Headquarters: San Jose, United States

Founded: 2022

Website LinkedIn Glassdoor

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Etched

1 month ago

Formal Verification - DV

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 5 hours agoStatus: Live

Job Summary

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Software Engineering

Key Responsibilities

•Define and drive formal verification strategy across the ASIC DV team for complex IP blocks, interface subsystems, and SoC integration logic.
•Develop formal verification plans covering functional correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom.
•Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models.
•Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics to establish formal sign-off confidence.
•Work with architects and RTL designers to translate design intent and specifications into high-value formal properties and closure criteria.

Pay and Benefits

Perks:MedicalDentalVisionHousing SubsidyRelocationMeal Allowance

Key Requirements

•5+ years of design verification experience with significant hands-on formal verification on complex digital designs or shipping silicon.
•Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology.
•Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.
•Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces.
•Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models.

Experience:5+ yearsSemiconductorsASICHardware

Skills:SystemVerilogSystemVerilog AssertionsUVM DVVerilogPCIeEthernetNoCsDMASoC

Languages:English

Tech Stack:SystemVerilogSystemVerilog AssertionsCadence JasperGoldSynopsys VC FormalSiemens Questa FormalUVMVerilogPCIeEthernetNoCsDMA

Company Brief

Etched

Industry: Hardware Devices

Company Size: Medium (51 to 250 employees)

Growth: Early Stage Startup

Valuation: Unicorn (USD 1B+)

Funding: Series A

Headquarters: San Jose, United States

Founded: 2022

Website LinkedIn Glassdoor