Physical Design Lead(High Speed IP's)

AMD
Bengaluru
Workplace: OnsiteFull timeINR 4,860,800 - 6,944,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: mastersSkills: ["Leadership","Mentoring","Cross-functional collaboration","Continuous improvement","Technical problem-solving"]

Drive physical implementation of high-speed interface IPs for advanced semiconductor platforms, including DDR/LPDDR/GDDR and PCIe/SerDes PHYs. Lead end-to-end flows across floorplanning, power planning, placement, clock architecture/CTS, timing and signal integrity closure, physical verification, and tapeout signoff. Partner with architects, RTL, AMS, package, SI/PI, SoC, and CAD/EDA vendors while mentoring engineers and improving automation, AI-assisted design methodologies, and signoff flows.

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FursaFursa
AMD
AMD
3 hours ago

Physical Design Lead(High Speed IP's)

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Reposted: similar role first listed 1 month ago

Job Summary

Drive physical implementation of high-speed interface IPs for advanced semiconductor platforms, including DDR/LPDDR/GDDR and PCIe/SerDes PHYs. Lead end-to-end flows across floorplanning, power planning, placement, clock architecture/CTS, timing and signal integrity closure, physical verification, and tapeout signoff. Partner with architects, RTL, AMS, package, SI/PI, SoC, and CAD/EDA vendors while mentoring engineers and improving automation, AI-assisted design methodologies, and signoff flows.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Lead physical design implementation of complex high-speed IPs such as DDR/LPDDR/GDDR PHYs, PCIe, and SerDes, including related subsystems.
  • •Own end-to-end physical implementation activities including floorplanning, power planning, placement, clock architecture, CTS, timing closure, and signal integrity closure.
  • •Drive physical verification and tapeout signoff for advanced-node designs, achieving aggressive PPA, frequency, power, and schedule goals.
  • •Partner with architects and circuit designers to optimize PHY architectures for performance, power, and implementation efficiency.
  • •Develop and deploy innovative implementation methodologies and lead continuous improvement via automation, AI-assisted design methodologies, and signoff flow enhancements.

Pay and Benefits

Salary: INR 4,860,800 - 6,944,000 annually

Key Requirements

  • •10+ years of physical design experience for advanced semiconductor products, including delivering multiple tape-outs.
  • •Deep expertise in high-speed digital and mixed-signal physical design implementation, including timing and clock distribution challenges.
  • •Experience with floorplanning, power planning, placement, clock architecture, CTS, and signoff/physical verification.
  • •Strong knowledge of STA and timing closure, signal integrity closure, and related analyses.
  • •Expertise with industry EDA tools including Cadence and Synopsys implementation/signoff flows; experience driving methodology development and automation.
Experience:10+ yearsSemiconductorPhysical designTape-outEDA
Education:Master's in Electrical Engineering, Computer Engineering, VLSI Design, or related field
Skills:LeadershipMentoringCross-functional collaborationContinuous improvementTechnical problem-solving
Languages:En-us
Tech Stack:CadenceSynopsysSTATclPythonUPF/CPFAI-assisted design flows

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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