3rd Party Memory PHY Technical Lead

AMD
Austin
Workplace: HybridFull timeUSD 126,700 - 217,200 annuallyFunction: Administration & Executive AssistanceSkills: ["Self-motivated","Problem-solving","Analytical","Attention to detail","Teamwork"]

Own the integration and support of third-party Memory/Serdes PHY and mixed-signal IP across multiple AMD product programs. Provide technical leadership from architecture through post-silicon validation and production, partnering with IP vendors and SoC integration teams to ensure signal, physical, and electrical quality. Drive system-level tradeoffs, interpret standards and customer requirements, and support bring-up, debug, characterization, compliance testing, and customer issue resolution while evaluating new PHY technologies for adoption.

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FursaFursa
AMD
AMD
2 days ago

3rd Party Memory PHY Technical Lead

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Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Own the integration and support of third-party Memory/Serdes PHY and mixed-signal IP across multiple AMD product programs. Provide technical leadership from architecture through post-silicon validation and production, partnering with IP vendors and SoC integration teams to ensure signal, physical, and electrical quality. Drive system-level tradeoffs, interpret standards and customer requirements, and support bring-up, debug, characterization, compliance testing, and customer issue resolution while evaluating new PHY technologies for adoption.
Location: Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Serve as the AMD technical owner for selected third-party Memory/Serdes PHY and mixed-signal IP across multiple product programs.
  • •Provide IP/PHY technical leadership across the product lifecycle from architecture through integration, post-silicon validation, and production.
  • •Collaborate with third-party IP vendors on evaluation, design transfer, release collateral, and integration into AMD SoCs with the Technical Project Manager.
  • •Partner with SoC integration teams to ensure electrical, logical, and physical quality of IP integration.
  • •Support post-silicon bring-up, debug, characterization, compliance testing, ATE production test support, customer issue resolution, and drive improvements to future PHY architectures and processes.

Pay and Benefits

Salary: USD 126,700 - 217,200 annually

Key Requirements

  • •Strong experience designing high-speed mixed-signal IP with system-level architecture and integration into an SoC.
  • •Knowledge of high-speed I/O SerDes or Memory PHY architectures and blocks (e.g., CTLE, FFE/DFE, VGA, CDR, PLL/DLL, TX driver, EMC, GPIO).
  • •Experience with one or more interface protocols such as HBM, LPDDR, DDR, GDDR, PCIe, Ethernet, USB, DisplayPort, HDMI, or MIPI.
  • •Understanding of RTL, logic design, and digital circuits, plus familiarity with UNIX environment.
  • •B.S. or M.S. in Electrical Engineering preferred; laboratory experience with equipment like BERT, oscilloscope, and logic analyzer is desirable.
Experience:SemiconductorsMixed-signalSoC integration
Education:
Skills:Self-motivatedProblem-solvingAnalyticalAttention to detailTeamwork
Languages:En-us
Tech Stack:PythonPerlUNIXBERTOscilloscopeLogic analyzerFinFETRTLCTLEFFEDFEVGACDRPLL/DLLTX driverEMCGPIOHBMLPDDRDDR

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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