Sr Principal Design Engineer
Cadence Design Systems
San Jose
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: phdSkills: ["Cadence","MATLAB","Python","SystemVerilog","VerilogA","C","PLL","DLL","CDR","ASIC","VLSI","Signal processing"]Join a seasoned team of engineers developing physical IP for high-speed serial links. As a Sr Principal Design Engineer, you will lead mixed-signal circuit design, verification, and testing from architectural specs, coordinate with the digital team, and contribute to post-silicon test plans and performance closure. You will work across analog/mixed-signal flows, mentor junior engineers, and influence architecture decisions in advanced process technologies.
