Sr Principal Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Verilog","SystemVerilog","PCIe","AXI","DMA","MSI","CDC","Asynchronous FIFO","Synthesis","Linting","Static timing analysis","Formal verification","Waveform debugging"]

We are seeking a highly skilled RTL Design Engineer with deep expertise in PCIe protocol (Gen4/Gen5/Gen6) to join our PCIe Controller IP development team. The candidate will design, implement, and verify RTL for PCIe controllers and related subsystems, ensuring protocol compliance and performance targets, while collaborating with system architects, verification teams, and cross-functional groups to optimize power, area, and timing.

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Cadence Design Systems
Cadence Design Systems
7 months ago

Sr Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live
Reposted: similar role first listed 9 months ago

Job Summary

We are seeking a highly skilled RTL Design Engineer with deep expertise in PCIe protocol (Gen4/Gen5/Gen6) to join our PCIe Controller IP development team. The candidate will design, implement, and verify RTL for PCIe controllers and related subsystems, ensuring protocol compliance and performance targets, while collaborating with system architects, verification teams, and cross-functional groups to optimize power, area, and timing.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Architect and implement RTL for PCIe IP blocks.
  • •Collaborate with system architects to define micro-architecture and design specifications.
  • •Interface with cross-functional teams including PHY, software, and validation.
  • •Work closely with verification teams to develop testbenches and validate functionality.
  • •Participate in interoperability testing and contribute to performance, power, and area optimization in advanced nodes.

Key Requirements

  • •Strong hands-on experience in RTL design using Verilog/SystemVerilog.
  • •Deep understanding of PCIe protocol stack and transaction layers.
  • •Experience with AXI & PXC interfaces, DMA engines, and MSI interrupt handling.
  • •Familiarity with CDC design principles and asynchronous FIFO implementation.
  • •Proficiency in synthesis, linting, and static timing analysis.
Experience:SemiconductorHardware designPCIe
Education:Bachelor's in Electronics / Electrical Engineering
Skills:VerilogSystemVerilogPCIeAXIDMAMSICDCAsynchronous FIFOSynthesisLintingStatic timing analysisFormal verificationWaveform debugging
Tech Stack:VerilogSystemVerilogPCIeAXIDMAMSICDCAsynchronous FIFOSynthesisLintingSTIFormal verificationWaveform debugging

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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