Static Timing Analysis Engineer

Intel
India
Workplace: HybridFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsEducation: bachelorsSkills: ["Collaboration","Continuous learning","Problem-solving","Technical expertise"]

Advance Intel’s next-generation SoCs by performing timing analysis and optimization at the chip and block levels. Generate and verify timing constraints, resolve timing violations, run timing rollups, and implement power-optimized clock networks aligned to high-performance/low-power guidelines. Define methodologies for high-quality timing models, set PVT conditions, and collaborate with architecture, clock, logic, and backend teams to deliver efficient partitioning and validated integration flows.

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Intel
Intel
4 months ago

Static Timing Analysis Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Advance Intel’s next-generation SoCs by performing timing analysis and optimization at the chip and block levels. Generate and verify timing constraints, resolve timing violations, run timing rollups, and implement power-optimized clock networks aligned to high-performance/low-power guidelines. Define methodologies for high-quality timing models, set PVT conditions, and collaborate with architecture, clock, logic, and backend teams to deliver efficient partitioning and validated integration flows.
Location: India
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Perform timing analysis and optimization to ensure design functionality and performance at chip and block levels.
  • •Generate and verify timing constraints; address and resolve timing violations during SoC development.
  • •Conduct timing rollups and develop/implement power-optimized clock networks aligned with high-performance and low-power guidelines.
  • •Define and implement methodologies to deliver quality timing models that improve the physical design process.
  • •Set PVT conditions for timing analysis and collaborate across architecture, clock, logic, and backend teams to achieve clocking balance and power delivery optimization.

Key Requirements

  • •Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
  • •8+ years of experience in Physical Design (or 6+ years with a Master’s / 4+ years with a PhD).
  • •Proficiency in static timing analysis tools and methodologies.
  • •Expertise in timing modeling, verification, constraint generation, and optimization techniques.
  • •Understanding of PVT conditions and how they apply to timing analysis.
Experience:8+ yearsSoC developmentPhysical designHigh-performance computingLow-power design
Education:Bachelor's
Skills:CollaborationContinuous learningProblem-solvingTechnical expertise

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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