RTL Intern

An RTL Intern design-ing microarchitecture and implementing logic in verilog for cutting-edge AI inference hardware. You’ll contribute to RTL block development, participate in the full design cycle from microarchitecture discussions to synthesis and timing feedback, and learn quickly in a high-autonomy environment with mentorship from industry leaders. Based in San Jose, CA, with exposure to ASIC/SoC design concepts and ML hardware.