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7 hours ago

Physical Design Engineer - Block Level, Subsystem Implementation

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Own block-level physical design for AI inference clusters, taking implementations from synthesis through GDSII sign-off. Drive block-level PPA optimization and timing closure across corners and modes, performing STA debug and ECO execution. Handle sign-off on EM/IR drop, RC extraction/correlation, and physical verification (DRC/LVS/antenna), and generate abstracts/views/timing budgets for hierarchical integration. Collaborate with RTL designers and supervise outsourced physical design work to ensure quality and closure.

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Own block-level and/or subsystem physical design end-to-end, including floorplanning, synthesis, placement, CTS, routing, and sign-off through GDSII.
•Drive block-level timing closure across corners and modes, including constraint development, STA debug, and functional/timing ECO implementation.
•Perform block-level sign-off across EM, IR drop, RC extraction/correlation, and physical verification (DRC, LVS, antenna).
•Create abstracts, views, and timing budgets to enable hierarchical integration of blocks into the top level.
•Collaborate with RTL designers on Physical Design feedback to improve PPA and supervise outsourced physical design work for quality and closure.

Pay and Benefits

Perks:Health InsuranceDentalVisionHousing SubsidyRelocation SupportWellness StipendMeal AllowanceDaily DinnerUnlimited Compute

Key Requirements

•5-10+ years of previous experience with physical design (PD).
•Experience with back-end physical design and timing closure on advanced process nodes (5nm and below).
•Tools and flow from RTL synthesis to GDSII sign-off, including constraint development and STA debug.
•Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) RTL-to-GDSII automated flows and sign-off tools (PrimeTime, Tempus, Voltus).
•Experience with UPF-based low power methodology and relevant verification/sign-off (e.g., scan insertion/ATPG, formal verification, EM/antenna analysis).

Experience:5-10 yearsAI hardwareFrontier inferenceASIC designRTL-to-GDSIIAdvanced process nodes

Skills:CollaborationTiming closureAttention to qualityProblem-solvingThinking from first principles

Tech Stack:GDSIICadence InnovusCadence GenusSynopsys Fusion CompilerPrimeTimeTempusVoltusTclPythonPerlUPFSTADRCLVSUPF-based low power designIR dropEM analysisAntenna analysisRC extractionFunctional ECO

Company Brief

Etched

Designs transformer‑specialized AI inference ASICs (product: Sohu) to accelerate large‑language‑model workloads, working with TSMC for fabrication and targeting energy‑efficient inference performance.

Industry: Hardware Devices

Company Size: Medium (51 to 250 employees)

Growth: Early Stage Startup

Valuation: Unicorn (USD 1B+)

Funding: Series A

Headquarters: San Jose, United States

Founded: 2022

Website LinkedIn Glassdoor

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Etched

7 hours ago

Physical Design Engineer - Block Level, Subsystem Implementation

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Own block-level and/or subsystem physical design end-to-end, including floorplanning, synthesis, placement, CTS, routing, and sign-off through GDSII.
•Drive block-level timing closure across corners and modes, including constraint development, STA debug, and functional/timing ECO implementation.
•Perform block-level sign-off across EM, IR drop, RC extraction/correlation, and physical verification (DRC, LVS, antenna).
•Create abstracts, views, and timing budgets to enable hierarchical integration of blocks into the top level.
•Collaborate with RTL designers on Physical Design feedback to improve PPA and supervise outsourced physical design work for quality and closure.

Pay and Benefits

Perks:Health InsuranceDentalVisionHousing SubsidyRelocation SupportWellness StipendMeal AllowanceDaily DinnerUnlimited Compute

Key Requirements

•5-10+ years of previous experience with physical design (PD).
•Experience with back-end physical design and timing closure on advanced process nodes (5nm and below).
•Tools and flow from RTL synthesis to GDSII sign-off, including constraint development and STA debug.
•Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) RTL-to-GDSII automated flows and sign-off tools (PrimeTime, Tempus, Voltus).
•Experience with UPF-based low power methodology and relevant verification/sign-off (e.g., scan insertion/ATPG, formal verification, EM/antenna analysis).

Experience:5-10 yearsAI hardwareFrontier inferenceASIC designRTL-to-GDSIIAdvanced process nodes

Skills:CollaborationTiming closureAttention to qualityProblem-solvingThinking from first principles

Company Brief

Etched

Industry: Hardware Devices

Company Size: Medium (51 to 250 employees)

Growth: Early Stage Startup

Valuation: Unicorn (USD 1B+)

Funding: Series A

Headquarters: San Jose, United States

Founded: 2022

Website LinkedIn Glassdoor