Design Verification Engineer

AMD
Vancouver
Workplace: HybridFull timeCAD 92,400 - 158,400 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Collaboration","Technical leadership","Problem-solving","Fast-paced execution"]

Verify complex PCI Express (PCIe) IP and subsystem designs for next-generation high-performance computing and semiconductor products. Develop scalable SystemVerilog/UVM verification environments, reusable verification components, and constrained-random/directed test suites. Drive coverage closure using functional, code, and assertion metrics, debug simulation/regression issues, and support verification signoff through silicon bring-up while collaborating across architecture, design, and validation teams.

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FursaFursa
AMD
AMD
6 days ago

Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Verify complex PCI Express (PCIe) IP and subsystem designs for next-generation high-performance computing and semiconductor products. Develop scalable SystemVerilog/UVM verification environments, reusable verification components, and constrained-random/directed test suites. Drive coverage closure using functional, code, and assertion metrics, debug simulation/regression issues, and support verification signoff through silicon bring-up while collaborating across architecture, design, and validation teams.
Location: Vancouver
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Develop, review, and execute comprehensive verification plans to ensure feature and functional coverage.
  • •Design and implement scalable SystemVerilog and UVM verification environments.
  • •Create reusable verification components (UVCs, BFMs, models, monitors, and checkers).
  • •Develop, maintain, and execute constrained-random and directed test suites; drive coverage closure using functional, code, and assertion metrics.
  • •Debug simulation and regression failures, reproduce silicon-reported issues in simulation, and support verification signoff through silicon bring-up.

Pay and Benefits

Salary: CAD 92,400 - 158,400 annually

Key Requirements

  • •Strong experience with SystemVerilog and UVM-based verification methodologies.
  • •Experience developing verification environments, testbench architectures, and reusable verification components.
  • •Knowledge of RTL design concepts and Verilog HDL.
  • •Experience with ASIC or SoC verification flows.
  • •Programming and scripting experience (C/C++, Java, and/or Perl, Python, Ruby, Shell) in Linux/UNIX environments.
Experience:ASIC verificationSoC verificationEDASemiconductor
Education:Master's in Electrical or computer engineering
Skills:CollaborationTechnical leadershipProblem-solvingFast-paced execution
Tech Stack:SystemVerilogUVMVerilog HDLPCI Express (PCIe)CC++JavaPerlPythonRubyShellLinux/UNIXVCSXcelium/NCSIMQuestaVerdiRTLASICSoCAXI

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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