Senior/Staff Digital Design Engineer

Olix
Austin, Bristol
Workplace: OnsiteFull timeUSD 194,000 - 270,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsSkills: ["Communication","Cross-functional collaboration","Mentoring","Leadership","Problem-solving"]

Senior/Staff Digital Design Engineer responsible for end-to-end CMOS digital design of high-speed, real-time data-processing silicon (OTPU). You will own RTL development, FPGA prototyping, algorithm modelling, PPA analysis, and cross-functional collaboration with optical, mixed-signal and software teams to deliver high-performance AI hardware.

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Olix
Olix
7 months ago

Senior/Staff Digital Design Engineer

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Job Summary

Senior/Staff Digital Design Engineer responsible for end-to-end CMOS digital design of high-speed, real-time data-processing silicon (OTPU). You will own RTL development, FPGA prototyping, algorithm modelling, PPA analysis, and cross-functional collaboration with optical, mixed-signal and software teams to deliver high-performance AI hardware.
Location: Austin, Bristol
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Architect, design and implement high‑throughput digital pipelines (multi‑GSPS input rate, continuous streaming data paths, deep pipelining and hand‑shaking) in advanced CMOS nodes.
  • •Prototype and iterate rapidly in FPGA (Xilinx/AMD, Intel, or equivalent): bring‑up real‑time demos, exercise high‑speed transceivers, and feed learnings back into the ASIC.
  • •Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate‑level sign‑off.
  • •Own RTL development (SystemVerilog / Verilog / VHDL) including synthesis, static‑timing closure, formal and constrained‑random verification.
  • •Analyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidth‑per‑watt targets.
  • •Collaborate with optical‑hardware, mixed‑signal and software teams to optimise data‑converter interfaces, clock‑domain crossings and firmware abstractions.
  • •Mentor junior engineers, lead design reviews and champion best‑practice design methodologies.

Pay and Benefits

Salary: USD 194,000 - 270,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kTime OffLife InsuranceDisabilityRetirement

Key Requirements

  • •7+ years of hands-on digital design for high-performance ASICs or SoCs, including ownership of at least one product that processes a continuous real-time data stream
  • •Proven success closing timing on multi-hundred-MHz to multi-GHz clock domains and integrating high-speed IP (e.g., SerDes, HBM/DDR, PCIe, 100 GbE or similar)
  • •Expertise with industry-standard EDA flows: RTL synthesis, CDC/RDC, STA, power-intent (UPF/CPF), lint, and gate-level simulation
  • •Demonstrated FPGA prototyping skills: constraint management, transceiver tuning, and hardware debug in the lab
  • •Proficiency using MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis and test-vector generation
Experience:7+ yearsSemiconductorsASICAI hardware
Skills:CommunicationCross-functional collaborationMentoringLeadershipProblem-solving
Languages:English
Tech Stack:MATLABSimulinkSystemVerilogVerilogVHDLFPGAXilinxAMDIntelSerDesHBMDDRPCIe100GbEPythonNumPyRTLSynthesisUPFCPF

Eligibility

Work Authorization:Sponsorship available.

Company Brief

Olix
Olix designs and manufactures optical processors (Optical Tensor Processing Units) for training and running inference on large AI models, aiming to deliver higher performance and lower energy consumption than conventional silicon-based accelerators.
Industry: Deep Tech
Company Size: Medium (51 to 250 employees)
Growth: Early Stage Startup
Headquarters: London, United Kingdom
Founded: 2024
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