Design Engineer II

Cadence Design Systems
Nanjing
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: bachelorsSkills: ["Communication","Cross-functional collaboration","Self-starter","Independent execution","Prioritization"]

Develop and advance high-performance physical IP for industry protocols, focusing on frontend/IP design for advanced Consumer PHYs. Implement and refine RTL features, support low-power design concepts, and collaborate on specification definition and test strategy. Partner with digital verification, analog, layout, backend, and lab bring-up/validation teams to deliver IP on schedule and provide pre/post-silicon application support for global customers.

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Cadence Design Systems
Cadence Design Systems
2 hours ago

Design Engineer II

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Develop and advance high-performance physical IP for industry protocols, focusing on frontend/IP design for advanced Consumer PHYs. Implement and refine RTL features, support low-power design concepts, and collaborate on specification definition and test strategy. Partner with digital verification, analog, layout, backend, and lab bring-up/validation teams to deliver IP on schedule and provide pre/post-silicon application support for global customers.
Location: Nanjing
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Entry level

Key Responsibilities

  • •Serve as a contributor and senior technical engineer in the IP frontend design team for high-performance Consumer PHYs.
  • •Implement RTL and refine features/requirements throughout the design process.
  • •Apply knowledge of synthesis, constraint generation, power management, and DFT, including low-power design techniques.
  • •Coordinate with digital verification on coverage points, testing strategy, corner conditions, and stimulus creation, including FPGA/Palladium testing.
  • •Partner with project management and multiple engineering teams to complete IP deliverables and provide pre/post-silicon application support.

Key Requirements

  • •MS or BS in Electrical/Computer Engineering or a related degree.
  • •1+ years of relative industry working experience.
  • •Good knowledge of best practices and flows in RTL design/verification and ASIC end-to-end methodology.
  • •Knowledge of one or more industry serial standards such as USB, DP, PCIe, or Ethernet.
  • •Strong cross-functional communication skills in English and Mandarin with a self-starter mindset.
Experience:1+ yearsASICSemiconductorIP development
Education:Bachelor's in Electrical/Computer Engineering or related degree
Skills:CommunicationCross-functional collaborationSelf-starterIndependent executionPrioritization
Languages:EnglishMandarin
Tech Stack:RTLSystem VerilogPythonC/C++ASIC design toolsSynthesisConstraint generationDFTLow-power designPower islandsState retentionIsolationDigital verificationFPGAPalladiumUSBUSB4PCIeDPEDP

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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