FCT PD lead

AMD
Bengaluru
Workplace: OnsiteFull timeINR 4,860,800 - 6,944,000 annuallyFunction: Administration & Executive AssistanceExperience: 14+ yearsEducation: mastersSkills: ["Communication","Problem-solving","Technical leadership","Mentoring"]

Lead Full Chip Timing (FCT) execution and timing signoff for complex SoC and subsystem designs. Own end-to-end timing closure for integration projects, develop SDC constraints and timing methodologies, and drive timing convergence through synthesis, P&R, CTS, routing, and ECO stages. Partner with Architecture and STA teams on timing budgets and signoff criteria, manage advanced-node timing margins and variation-aware signoff, and lead planning to ensure on-time tapeout while mentoring engineers.

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FursaFursa
AMD
AMD
1 week ago

FCT PD lead

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Last checked: 16 hours agoStatus: Live

Job Summary

Lead Full Chip Timing (FCT) execution and timing signoff for complex SoC and subsystem designs. Own end-to-end timing closure for integration projects, develop SDC constraints and timing methodologies, and drive timing convergence through synthesis, P&R, CTS, routing, and ECO stages. Partner with Architecture and STA teams on timing budgets and signoff criteria, manage advanced-node timing margins and variation-aware signoff, and lead planning to ensure on-time tapeout while mentoring engineers.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead the Full Chip Timing team for timing constraints development and timing signoff.
  • •Own end-to-end timing closure and signoff for SoC and subsystem integration projects.
  • •Define, develop, and validate SDC constraints, clocks, and timing methodologies across design stages.
  • •Drive timing convergence through synthesis, P&R, CTS, routing, and post-route ECO stages to ensure timing closure.
  • •Manage advanced-node timing margins and variation-aware signoff methodologies; lead timing ECO planning and execution and mentor engineers.

Pay and Benefits

Salary: INR 4,860,800 - 6,944,000 annually

Key Requirements

  • •14+ years of experience in Physical Design, Static Timing Analysis, Constraints Development, and Timing Signoff.
  • •Strong expertise in Full Chip Timing Closure and STA Signoff.
  • •Deep knowledge of Timing Constraints (SDC), Clock Architecture/Implementation, and MCMM Timing Analysis.
  • •Experience with timing ECO methods and advanced-node timing signoff, including LVF/SSTA and OCV/AOCV/POCV approaches.
  • •Hands-on tooling experience with Synopsys PrimeTime (PT) and GCA; Fusion Compiler and/or ICC2 is highly desirable.
Experience:14+ years
Education:Master's in computer engineering/Electrical Engineering
Skills:CommunicationProblem-solvingTechnical leadershipMentoring
Languages:En-us
Tech Stack:Synopsys PrimeTime (PT)GCAFusion CompilerICC2SDCTclPerlShellPythonLVFSSTAOCV/AOCV/POCVMCMMDFT

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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