Senior Software Engineer - Low Power Verification

Cadence Design Systems
Taiwan
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 4+ yearsSkills: ["Root-cause analysis","Critical evaluation","Debugging","Object-oriented reasoning","Performance improvement"]

Build and optimize low-power verification software for Palladium and Protium emulation and prototyping platforms. You will improve UPF waveform generation accuracy and performance across PPC and MC flows (including Dielet UPF), enhance SAGE-based UPF debug with Verisium, and develop AI-assisted UPF debug tools. Collaborate with R&D, PE, and AE teams to deploy UPF solutions and consolidate UPF debug across Palladium and Protium.

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Cadence Design Systems
Cadence Design Systems
5 days ago

Senior Software Engineer - Low Power Verification

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Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live

Job Summary

Build and optimize low-power verification software for Palladium and Protium emulation and prototyping platforms. You will improve UPF waveform generation accuracy and performance across PPC and MC flows (including Dielet UPF), enhance SAGE-based UPF debug with Verisium, and develop AI-assisted UPF debug tools. Collaborate with R&D, PE, and AE teams to deploy UPF solutions and consolidate UPF debug across Palladium and Protium.
Location: Taiwan
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Mid level

Key Responsibilities

  • •Improve performance and correctness of UPF waveform generation across PPC and MC flows, including Dielet UPF support.
  • •Enhance SAGE-based UPF debug with Verisium to improve performance and usability.
  • •Develop AI-assisted, Verisium-integrated UPF debug tools to reduce time-to-root-cause for low-power design issues.
  • •Work with R&D, PE, and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, Dielets) with UPF in 2- and 4-state modes.
  • •Consolidate and unify UPF debug across Palladium and Protium.

Key Requirements

  • •BS in CS, EE, or related field with 4+ years of experience (MS with 2+ years; PhD with 1+ year) or equivalent practical experience.
  • •Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
  • •Strong debugging skills for root-cause analysis from logs, waveforms, traces, testcases, and user reports.
  • •Ability to read, review, and reason about C++ code and object-oriented designs.
  • •Scripting experience in Perl, Tcl/Tk, and/or Python, plus fluency with AI-assisted coding tools with critical evaluation of AI output.
Experience:4+ years
Education:
Skills:Root-cause analysisCritical evaluationDebuggingObject-oriented reasoningPerformance improvement
Tech Stack:UPFIEEE 1801VerilogSystemVerilogVHDLC++PerlTcl/TkPythonAI-assisted coding toolsCopilotClaudeCursorPalladiumProtiumParallel Partition Compiler (PPC)Modular Compiler (MC)UPF waveform generationDielet UPFSAGE

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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