Cadence Design Systems

1 day ago

Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 6 hours agoStatus: Live

Job Summary

Design, develop, and support system-level memory IP models for hardware-based verification products, including SDRAM, NAND Flash, eMMC, SD Card, DFI, and UFS. Update and document existing memory model products and perform as an individual contributor across RTL design, verification, productizing, and documentation. Collaborate with internal and external customers on emulation/simulation/verification problems, and support cross verification and lifecycle processes to drive product quality.

Location: Shanghai

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Schedule, design, develop, and support system-level memory IP models for hardware-based verification products.
•Update, maintain, document, and support existing system-level memory model products.
•Act as an individual contributor for RTL design, verification, productizing, and documentation of memory IP.
•Interface with internal and external customers to solve problems related to emulation, simulation, and verification.
•Contribute to cross verification and cross training in memory IP, and help develop lifecycle processes to ensure product quality.

Key Requirements

•MSEE (or equivalent) with at least 5 years of experience designing complex protocols and/or hardware systems.
•Fluent, extensive RTL design knowledge using Verilog/SystemVerilog, plus experience with RTL verification tools and flows.
•Strong debugging skills in support of hardware design and verification.
•Excellent written and spoken English communication skills.
•Collaborative, emotionally intelligent teamwork with experience using team-wide collaboration tools and processes.

Experience:5+ yearsHardware verificationMemory IPSemiconductor

Education:Master's

Skills:CommunicationDebuggingCollaborationPlanningAdaptability

Languages:English

Tech Stack:VerilogSystemVerilogRTLRTL verification toolsSimulationEmulationPerlTCLC-shellCadence simulationCadence emulation

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

1 day ago

Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 6 hours agoStatus: Live

Job Summary

Location: Shanghai

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Schedule, design, develop, and support system-level memory IP models for hardware-based verification products.
•Update, maintain, document, and support existing system-level memory model products.
•Act as an individual contributor for RTL design, verification, productizing, and documentation of memory IP.
•Interface with internal and external customers to solve problems related to emulation, simulation, and verification.
•Contribute to cross verification and cross training in memory IP, and help develop lifecycle processes to ensure product quality.

Key Requirements

•MSEE (or equivalent) with at least 5 years of experience designing complex protocols and/or hardware systems.
•Fluent, extensive RTL design knowledge using Verilog/SystemVerilog, plus experience with RTL verification tools and flows.
•Strong debugging skills in support of hardware design and verification.
•Excellent written and spoken English communication skills.
•Collaborative, emotionally intelligent teamwork with experience using team-wide collaboration tools and processes.

Experience:5+ yearsHardware verificationMemory IPSemiconductor

Education:Master's

Skills:CommunicationDebuggingCollaborationPlanningAdaptability

Languages:English

Tech Stack:VerilogSystemVerilogRTLRTL verification toolsSimulationEmulationPerlTCLC-shellCadence simulationCadence emulation

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor