Silicon Design Engineer 2 - Multi subsystem verification

AMD
Shanghai
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Collaboration","Technical guidance","Process improvement","Innovation","Clear technical communication"]

Join the NBIO MPME team to drive multi-subsystem interoperability verification across PCIe and other NBIO interconnect subsystems. Port and create the DV environment for new designs, build and implement DV test plans, perform coverage analysis, and clean up regressions. Collaborate with global engineering teams on multiple programs and provide technical guidance to junior engineers, improving development process and innovation.

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FursaFursa
AMD
AMD
21 hours ago

Silicon Design Engineer 2 - Multi subsystem verification

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Source: Company careers pageValidated by: Fursa AI
Last checked: 10 hours agoStatus: Live

Job Summary

Join the NBIO MPME team to drive multi-subsystem interoperability verification across PCIe and other NBIO interconnect subsystems. Port and create the DV environment for new designs, build and implement DV test plans, perform coverage analysis, and clean up regressions. Collaborate with global engineering teams on multiple programs and provide technical guidance to junior engineers, improving development process and innovation.
Location: Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Port or create the DV environment for new designs and support DV environment setup.
  • •Create and implement DV test plans, including coverage analysis and regression cleanup.
  • •Collaborate with global engineering teams to implement multiple programs.
  • •Improve the development process and drive innovation within the team.
  • •Provide technical guidance to junior engineers.

Key Requirements

  • •Be involved in porting/creation of the DV environment for new designs, including test plan creation and implementation.
  • •Perform coverage analysis and regression cleanup to support verification quality and progress.
  • •Have solid knowledge of SystemVerilog, UVM, C/C++, and Verilog.
  • •Have hardware verification methodology experience, including coverage-based verification with hardware assertions (PSL or SVA).
  • •Have scripting skills in Perl, python, or ruby; knowledge of UPF/NLP and PCIe is a plus.
Education:Bachelor's in Computer engineering/Electrical Engineering
Skills:CollaborationTechnical guidanceProcess improvementInnovationClear technical communication
Languages:English
Tech Stack:SystemVerilogUVMCC++VerilogHardware assertionsPSLSVAPerlPythonRubyNLPUPFPCIeDV environmentDV test planCoverage analysisRegression cleanup

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn