Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Sunnyvale
Workplace: OnsiteFull timeUSD 170,000 - 230,000 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 5+ yearsEducation: bachelorsSkills: ["Calibre","ICV","Pegasus","Python","Bash","Perl","TCL"]Senior-level engineer responsible for full-chip physical verification of advanced ASIC/SOC designs, driving DRC/LVS/ESD/PER C signoffs, DRM interpretation, and signoff coordination with foundries and internal teams to ensure tapeout readiness for Starlink silicon platforms.
