ASIC Engineering Technical Leader | Design Verification | Verilog, System Verilog, UVM, Testbench | Exp- 12+ Years

Cisco
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 12+ yearsSkills: ["Leadership","Communication","Problem-solving","Mentoring","Teamwork"]

Lead verification efforts for advanced ASICs, architect and implement Verilog/SystemVerilog/UVM testbenches, and drive verification milestones. Collaborate with design teams to ensure functional coverage and robust test environments. Mentor engineers, troubleshoot complex failures, and ensure on-time delivery of verified designs in a high-performance hardware environment.

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FursaFursa
Cisco
Cisco
2 months ago

ASIC Engineering Technical Leader | Design Verification | Verilog, System Verilog, UVM, Testbench | Exp- 12+ Years

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Lead verification efforts for advanced ASICs, architect and implement Verilog/SystemVerilog/UVM testbenches, and drive verification milestones. Collaborate with design teams to ensure functional coverage and robust test environments. Mentor engineers, troubleshoot complex failures, and ensure on-time delivery of verified designs in a high-performance hardware environment.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Lead the verification strategy and plan for ASIC blocks, and oversee the verification lifecycle from test plan to sign-off.
  • •Develop and maintain Verilog/SystemVerilog testbenches and UVM-based environments to validate complex designs.
  • •Collaborate with design teams to debug issues, close coverage gaps, and ensure functional correctness.
  • •Mentor and guide junior engineers, review verification code, and drive milestones across the project.
  • •Analyze verification results, diagnose failures, and provide actionable recommendations to improve design quality and delivery timelines.

Key Requirements

  • •12+ years of experience in ASIC/HDL-based design verification
  • •Expertise in Verilog and SystemVerilog
  • •Strong practice with UVM and UVM-based testbenches
  • •Proven track record leading a verification team or technical leadership role
  • •Excellent debugging, problem-solving, and collaboration skills
Experience:12+ yearsSemiconductorHardwareASICVLSI
Skills:LeadershipCommunicationProblem-solvingMentoringTeamwork
Tech Stack:VerilogSystemVerilogUVMTestbenchRTLVLSISoC

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
Glassdoor
Glassdoor: 4.0
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