Principal HIG ESD and Latch-up Engineer- HBM - TPG

Micron Technology
United States
Workplace: OnsiteFull timeUSD 175,000 - 297,000 annuallyFunction: Communications, PR & CommunityEducation: mastersSkills: ["Collaboration","Mentoring","Influencing"]

Own chip-level and IP-level ESD and latch-up protection strategies for next-generation HBM DRAM products, from early design through high-volume manufacturing. Define ESD requirements and sign-off criteria aligned to JEDEC/ESDA standards, enable safe protection circuit and layout practices, and validate via silicon bring-up, failure analysis, and correlation to pre-silicon assumptions. Partner with design, packaging, reliability, and foundries as the technical interface.

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FursaFursa
Micron Technology
Micron Technology
3 months ago

Principal HIG ESD and Latch-up Engineer- HBM - TPG

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Source: Company careers pageValidated by: Fursa AI
Last checked: 15 hours agoStatus: Live

Job Summary

Own chip-level and IP-level ESD and latch-up protection strategies for next-generation HBM DRAM products, from early design through high-volume manufacturing. Define ESD requirements and sign-off criteria aligned to JEDEC/ESDA standards, enable safe protection circuit and layout practices, and validate via silicon bring-up, failure analysis, and correlation to pre-silicon assumptions. Partner with design, packaging, reliability, and foundries as the technical interface.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community
Seniority: Sr. Manager level

Key Responsibilities

  • •Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, including base die, I/O, TSVs, and die-to-die interfaces.
  • •Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards.
  • •Enable ESD protection circuits and latch up safe layout practices across designs and technologies.
  • •Lead silicon validation, failure analysis, and correlation of pre-silicon assumptions to silicon results.
  • •Serve as the technical interface to foundries and partner with design, packaging, reliability, and product teams.

Pay and Benefits

Salary: USD 175,000 - 297,000 annually
Perks:Health InsuranceDentalVisionPaid LeavePaid Holidays

Key Requirements

  • •Master’s degree or Ph.D. in Electrical Engineering or equivalent industry experience.
  • •Strong fundamentals in ESD physics, latch up mechanisms, and advanced CMOS devices.
  • •Hands-on experience with ESD protection circuits and latch up prevention techniques.
  • •Familiarity with JEDEC and ESDA standards, including HBM, CDM, and JESD78.
  • •Experience supporting ESD and latch up sign-off for advanced DRAM or HBM products.
Experience:SemiconductorsDRAMHBMFoundries
Education:Master's in Electrical Engineering
Skills:CollaborationMentoringInfluencing
Tech Stack:HBMDRAMESDLatch upJEDECESDACDMJESD78CMOSSCR-based clamps

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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