CAD Developer, IR, Timing and Physical Design Optimization

NVIDIA
Shanghai
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 2+ yearsSkills: ["Communication","Interpersonal skills"]

Build and optimize physical-design infrastructure for advanced ASIC chips, owning workflows from discovery through deployment with design teams. Develop algorithms and tools to improve chip frequency while reducing power, including IR-drop optimization, simulation, timing analysis, and signoff-related flows. Write substantial C++ to enhance internal optimization toolchains, collaborating across ASIC/P&R/DFT/SI/ARCH teams to enable physical-friendly design at leading-edge process technology.

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FursaFursa
NVIDIA
NVIDIA
4 days ago

CAD Developer, IR, Timing and Physical Design Optimization

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 21 hours agoStatus: Live

Job Summary

Build and optimize physical-design infrastructure for advanced ASIC chips, owning workflows from discovery through deployment with design teams. Develop algorithms and tools to improve chip frequency while reducing power, including IR-drop optimization, simulation, timing analysis, and signoff-related flows. Write substantial C++ to enhance internal optimization toolchains, collaborating across ASIC/P&R/DFT/SI/ARCH teams to enable physical-friendly design at leading-edge process technology.
Location: Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering

Key Responsibilities

  • •Invent and optimize methods to increase chip frequency while minimizing power across internal optimization tools.
  • •Improve algorithms in C++ for IR drop optimization and simulation.
  • •Own the end-to-end process from discovery of optimization opportunities through developing solutions and working with design teams for deployment.
  • •Support physical design scope from RTL to GSDII including design quality check, synthesis, formal check, partitioning, constraints, async check, and timing analysis/fixing/signoff.
  • •Collaborate with ASIC/P&R/DFT/SI/ARCH teams to drive physical-friendly design across related workflows.

Key Requirements

  • •BS, MS, or PhD in Electrical Engineering or Computer Science, or equivalent experience.
  • •Minimum 2+ years of relevant experience in CAD software and VLSI hardware design.
  • •Strength in both CAD software and VLSI design.
  • •Understanding of VLSI IR drop optimization/simulation and related concepts (constraints, corners, CCSP, FSDB, etc.).
  • •Demonstrated software development ability using C++.
Experience:2+ yearsCAD softwareVLSI hardware designASIC-PDEDA
Education:
Skills:CommunicationInterpersonal skills
Tech Stack:C++C++14LambdasConcurrencyMultithreadingDistributed computingRedHawkPerlTclPythonIR drop optimizationSimulationFSDBCCSP

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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Glassdoor: 4.3
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