Mixed Signal Logic Design Engineer
Intel
Phoenix, Santa Clara
Workplace: OnsiteFull timeUSD 141,910 - 200,340 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 4+ yearsEducation: bachelorsSkills: ["SystemVerilog","RTL","Linting","CDC analysis","Analog design","Mixed-signal","Python","Perl","Bash","Scripting","UCIe","PCIe","USB","AMS","Synthesis","Timing closure"]Join Intel as a Mixed Signal Logic Design Engineer shaping high-speed mixed-signal IP designs. Lead architecture/microarchitecture definitions, implement RTL in SystemVerilog, model analog blocks, run AMS simulations, and collaborate across pre/post-silicon teams to meet power, performance, and area goals in full-chip designs.
