Lead Digital Design Engineer

Texas Instruments
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Communication","Stakeholder management","Focus","Mentoring","Leadership"]

Lead SoC Front End integration for an ARM-based SoC through RTM, owning complex integration activities and coordinating with systems, IP, and DV teams. Drive high-quality deliverables by running LEC, LINT checks, and CDC/RDC analysis, and ensure testability, reliability, and manufacturability. Partner with backend, DFT, and flow teams to plan SoC releases, and implement correct power intent via low-power checks like CLP.

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FursaFursa
Texas Instruments
Texas Instruments
3 months ago

Lead Digital Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 19 hours agoStatus: Live

Job Summary

Lead SoC Front End integration for an ARM-based SoC through RTM, owning complex integration activities and coordinating with systems, IP, and DV teams. Drive high-quality deliverables by running LEC, LINT checks, and CDC/RDC analysis, and ensure testability, reliability, and manufacturability. Partner with backend, DFT, and flow teams to plan SoC releases, and implement correct power intent via low-power checks like CLP.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead a SoC Front End team to own SoC integration of a complex ARM-based SoC up to RTM.
  • •Collaborate with systems, IP, and DV teams to align on feature updates and IP deliverables for timely SoC integration.
  • •Ensure functional, performance, safety, and security requirements are fully comprehended with the SoC system architect.
  • •Work with backend, DFT, and flow teams to create and plan SoC releases.
  • •Drive SoC integration quality via LEC, LINT checks, and CDC/RDC analysis, and ensure correct power intent using low-power checks like CLP.

Key Requirements

  • •Bachelor or Masters in EE/ECE/CS (or related) with 5+ years of experience in SoC/subsystem design or integration.
  • •Experience integrating SoCs and sub-systems.
  • •Strong system-level analysis experience, including understanding use case scenarios, and safety and security requirements.
  • •Experience with SoC power analysis and power optimization, including advanced low power design techniques.
  • •Good understanding of constraints development for Physical Design implementation and Static Timing Analysis; Design-for-Debug/Design-for-Test is desirable.
Experience:5+ yearsSemiconductorsSoC integration
Education:Bachelor's in EE/ECE/CS
Skills:CommunicationStakeholder managementFocusMentoringLeadership
Tech Stack:ARMSoCLECLINTCDCRDCCLPLow-PowerPhysical DesignStatic Timing AnalysisDesign-for-DebugDesign-for-Test

Company Brief

Texas Instruments
Designs and manufactures semiconductors and analog chips used in industrial, automotive, personal electronics, communications, and enterprise systems. It is one of the world’s largest semiconductor companies, with a broad portfolio of embedded processing and power products.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Dallas, United States
Founded: 1930
WebsiteLinkedIn