Sr Principal Design Engineer — Memory Modeling Portfolio

Cadence Design Systems
China
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: mastersSkills: ["Debugging","Methodical","Patience","Precision","Collaboration","Mentorship","Communication"]

Serve as a senior design engineering architect for Cadence’s Memory Model Portfolio (MMP) R&D team, acting as the primary Korea-based expert for the UFS/Unipro/MPHY/RMMI protocol stack. Partner directly with electronics and computing customers to deploy, debug, and integrate complex memory protocol IP using Palladium and Protium emulation platforms. Triage field issues, define actionable problem statements for R&D, and mentor engineers across RTL and verification methodology.

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Cadence Design Systems
Cadence Design Systems
2 days ago

Sr Principal Design Engineer — Memory Modeling Portfolio

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Last checked: 11 hours agoStatus: Live

Job Summary

Serve as a senior design engineering architect for Cadence’s Memory Model Portfolio (MMP) R&D team, acting as the primary Korea-based expert for the UFS/Unipro/MPHY/RMMI protocol stack. Partner directly with electronics and computing customers to deploy, debug, and integrate complex memory protocol IP using Palladium and Protium emulation platforms. Triage field issues, define actionable problem statements for R&D, and mentor engineers across RTL and verification methodology.
Location: China
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Serve as the primary customer interface for protocol integration, system-level debugging, and solutions consulting across the UFS/Unipro/MPHY/RMMI stack.
  • •Debug, characterize, and translate customer root-cause findings into clear, actionable problem definitions for the R&D team.
  • •Triage and analyze incoming field issues; scope, coordinate repair of model defects with R&D, and track issues to resolution.
  • •Analyze customer requirements and map them to MMP capabilities or feature gaps; present solutions to technical and managerial audiences.
  • •Mentor less experienced design engineers in protocol understanding, RTL code, and verification methodology; provide technically grounded RTL feedback and participate in reviews and quality processes.

Key Requirements

  • •Master’s degree in Electrical Engineering (or equivalent) with 10+ years of relevant experience, or PhD with 8+ years.
  • •Deep expertise in the UFS/Unipro/MPHY/RMMI protocol stack, with ability to debug across layers to pinpoint root cause.
  • •Fluent in SystemVerilog/Verilog RTL design and verification; able to write, review, and rigorously debug RTL constructs for hardware emulation environments.
  • •Advanced English written and verbal fluency for globally integrated communication.
  • •Proven debugging skill with methodical, patient, precise execution under customer pressure.
Experience:8+ yearsMemory modelingProtocolsHardware emulationVerification
Education:Master's in Electrical Engineering
Skills:DebuggingMethodicalPatiencePrecisionCollaborationMentorshipCommunication
Languages:English
Tech Stack:UFSUniproMPHYRMMISDRAMDDRxLPDDRxHBMxNAND FlashDFI PHYSystemVerilogVerilogRTLHardware emulationPalladiumProtiumPerlTCLC-shellRTL code

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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