FuriosaAI

3 weeks ago

Silicon Validation Engineer (NPU SoC)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 8 hours agoStatus: Live

Job Summary

Lead end-to-end system-level validation for NPU SoCs, driving 1st silicon bring-up and verifying core compute, NoC, memory (LPDDR/HBM), and high-speed interfaces (e.g., Ethernet). Define validation methodology and test plans across pre- and post-silicon environments, build bare-metal test firmware, and perform HW/SW co-debugging with JTAG/Trace32 to deliver workarounds. Support performance validation and automation via CI/CD-linked scripts.

Location: Seoul

Workplace: Onsite

Employment Type: Full time

Job Function: Healthcare (Clinical, Medical, Wellness)

Key Responsibilities

•Drive 1st silicon bring-up by validating NPU accelerator cores, CPU subsystem, NoC, and scenario-based functionality, including memory (LPDDR/HBM) and high-speed I/F (e.g., Ethernet) integration.
•Create and execute validation plans and manage coverage across pre-silicon (emulator/FPGA) and post-silicon environments.
•Write bare-metal test firmware for IP validation and develop test scenarios.
•Perform system-level issue debugging and derive workarounds for complex HW(RTL)/SW(firmware/driver) boundary issues using tools like JTAG and Trace32, then report to related teams.
•Support performance validation/optimization and build test automation scripts with CI/CD integration.

Key Requirements

•Experience with SoC/ASIC or complex silicon/system validation, including leadership-level experience for senior profiles.
•Strong understanding of ARM architecture, AMBA bus (AXI/AHB), and overall SoC/computer architecture.
•Embedded C/C++ and Rust programming skills for hardware control and IP testing in bare-metal environments.
•Knowledge and experience with validation methodology from test planning through bug tracking and coverage.
•JTAG debugging expertise (e.g., Trace32) and strong HW/SW co-debugging capability.

Experience:SoCASICSilicon validationNPUAI accelerators

Skills:Problem-solvingDebuggingLogical analysisCoverage managementWorkaround developmentCross-functional communication

Tech Stack:RTLDVFWOSNPUSoCASICARMAMBAAXIAHBBare-metalCC++RustJTAGTrace32EmulatorFPGAPalladium

Company Brief

FuriosaAI

Designs and develops data‑center AI inference accelerators (RNGD) and a full stack hardware‑software platform to deliver energy‑efficient, high‑performance AI compute for enterprise and cloud customers.

Industry: Hardware Devices

Company Size: Medium (51 to 250 employees)

Growth: Scaleup

Valuation: USD 500M to 1B

Funding: Series C

Headquarters: Seoul, South Korea

Founded: 2017

Glassdoor: 4.6

Website LinkedIn Glassdoor

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FuriosaAI

3 weeks ago

Silicon Validation Engineer (NPU SoC)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 8 hours agoStatus: Live

Job Summary

Location: Seoul

Workplace: Onsite

Employment Type: Full time

Job Function: Healthcare (Clinical, Medical, Wellness)

Key Responsibilities

•Drive 1st silicon bring-up by validating NPU accelerator cores, CPU subsystem, NoC, and scenario-based functionality, including memory (LPDDR/HBM) and high-speed I/F (e.g., Ethernet) integration.
•Create and execute validation plans and manage coverage across pre-silicon (emulator/FPGA) and post-silicon environments.
•Write bare-metal test firmware for IP validation and develop test scenarios.
•Perform system-level issue debugging and derive workarounds for complex HW(RTL)/SW(firmware/driver) boundary issues using tools like JTAG and Trace32, then report to related teams.
•Support performance validation/optimization and build test automation scripts with CI/CD integration.

Key Requirements

•Experience with SoC/ASIC or complex silicon/system validation, including leadership-level experience for senior profiles.
•Strong understanding of ARM architecture, AMBA bus (AXI/AHB), and overall SoC/computer architecture.
•Embedded C/C++ and Rust programming skills for hardware control and IP testing in bare-metal environments.
•Knowledge and experience with validation methodology from test planning through bug tracking and coverage.
•JTAG debugging expertise (e.g., Trace32) and strong HW/SW co-debugging capability.

Experience:SoCASICSilicon validationNPUAI accelerators

Skills:Problem-solvingDebuggingLogical analysisCoverage managementWorkaround developmentCross-functional communication

Tech Stack:RTLDVFWOSNPUSoCASICARMAMBAAXIAHBBare-metalCC++RustJTAGTrace32EmulatorFPGAPalladium

Company Brief

FuriosaAI

Industry: Hardware Devices

Company Size: Medium (51 to 250 employees)

Growth: Scaleup

Valuation: USD 500M to 1B

Funding: Series C

Headquarters: Seoul, South Korea

Founded: 2017

Glassdoor: 4.6

Website LinkedIn Glassdoor