Design Engineer I

Cadence Design Systems
United States
Full timeUSD 88,900 - 165,100 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["Problem-solving","Debugging","Cross-functional collaboration"]

Own the end-to-end DFT (Design for Test) implementation for complex SoC designs, from architecture definition to silicon testing and debug. Define and implement SoC-level DFT architecture, develop and support SCAN/ATPG/MBIST/BSCAN/iJTAG, and perform DFT insertion, verification, and coverage analysis. Lead pre-silicon sign-off with DRC closure and coverage targets, then support post-silicon failure analysis, yield learning, and cross-functional collaboration.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
3 days ago

Design Engineer I

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Source: Company careers pageValidated by: Fursa AI
Last checked: 18 hours agoStatus: Live

Job Summary

Own the end-to-end DFT (Design for Test) implementation for complex SoC designs, from architecture definition to silicon testing and debug. Define and implement SoC-level DFT architecture, develop and support SCAN/ATPG/MBIST/BSCAN/iJTAG, and perform DFT insertion, verification, and coverage analysis. Lead pre-silicon sign-off with DRC closure and coverage targets, then support post-silicon failure analysis, yield learning, and cross-functional collaboration.
Location: United States
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Define and implement SoC-level DFT architecture for large, complex designs.
  • •Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN, and iJTAG.
  • •Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
  • •Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
  • •Support post-silicon debug, failure analysis, and yield learning, collaborating with RTL, verification, physical design, and operations teams.

Pay and Benefits

Salary: USD 88,900 - 165,100 annually
Equity and Bonus:Equity
Perks:Paid LeavePaid Holidays401kMedicalDentalVisionEquity

Key Requirements

  • •BS degree.
  • •At least 3 years of hands-on experience in SoC DFT.
  • •Strong expertise in SCAN, ATPG, and MBIST.
  • •Experience with pre-silicon validation and post-silicon debug.
  • •Ability to work effectively in a cross-functional engineering environment.
Experience:3+ yearsSoC DFT
Education:Bachelor's
Skills:Problem-solvingDebuggingCross-functional collaboration
Tech Stack:SoC DFTSCANATPGMBISTBSCANIJTAGTCLPerlPythonRTLPhysical designDRCCoverage analysisSilicon testingFailure analysisSilicon yield

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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