Senior STA Design Engineer

AMD
Bengaluru
Workplace: OnsiteFull timeINR 2,186,520 - 3,123,600 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 4-5 yearsEducation: mastersSkills: []

Develop and maintain multi-mode, multi-corner timing constraints compatible with RTL and signoff. Ensure SDC quality using EDA tools (e.g., Fishtail, GCA), run pre-route timing checks, and drive QoR clean-up to resolve SDC issues. Lead timing closure for sub-chips or full chips, including interface timing closure and DRV closure, and generate timing ECOs using DMSA/Tweaker. Work with EDA timing flows and Tcl scripting.

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FursaFursa
AMD
AMD
23 hours ago

Senior STA Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 20 hours agoStatus: Live

Job Summary

Develop and maintain multi-mode, multi-corner timing constraints compatible with RTL and signoff. Ensure SDC quality using EDA tools (e.g., Fishtail, GCA), run pre-route timing checks, and drive QoR clean-up to resolve SDC issues. Lead timing closure for sub-chips or full chips, including interface timing closure and DRV closure, and generate timing ECOs using DMSA/Tweaker. Work with EDA timing flows and Tcl scripting.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Develop complex multi-mode/multi-corner timing constraints compatible with RTL and signoff.
  • •Ensure SDC constraints quality using industry tools like Fishtail and GCA.
  • •Drive pre-route timing checks and QoR clean-up to eliminate SDC issues and ensure quality handoff for STA checks.
  • •Perform timing closure for one or more sub-chips/subsystems or full chip, including subsystem/full-chip interface timing closure and DRV closure.
  • •Generate timing ECOs using tools DMSA/Tweaker.

Pay and Benefits

Salary: INR 2,186,520 - 3,123,600 annually

Key Requirements

  • •4-5 years building timing constraints for IPs, blocks, and full-chip implementation (flat/hierarchical flows).
  • •Experience analyzing timing reports to identify design and constraints-related issues.
  • •EDA tool experience such as Synopsys Design Compiler/PrimeTime and/or Spyglass, Fishtail, Tweaker.
  • •Strong Tcl scripting capability in both EDA environments and standalone Linux Tcl shell scripts.
  • •Good understanding of SDC constraints and analysis (OCV, AOCV, POCV) plus DFT modes for timing signoff.
Experience:4-5 years
Education:Master's in computer engineering / Electrical Engineering
Languages:En-us
Tech Stack:SDCFishtailGCATclLinuxSynopsys Design CompilerPrimeTimeSpyglassTweakerDMSADRV closureECOOCVAOCVPOCVDFT

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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