IC Design Engineer

Lead Broadcom’s physical design methodology to achieve right-first-time silicon. Work on block and level layout, floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification for SoCs in 5nm and beyond. Execute and close timing (STA) through P&R, extraction, and verification, implement timing/functional ECOs, and build or adapt automation flows using major EDA tools. Drive improvements in TAT with quality.