SR Design Verification Engineer
AMD
Santa Clara
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["SystemVerilog","UVM","Verilog","Verdi","DVE","Python","Tcl","Make"]Design Verification Engineer at AMD responsible for leading verification of high‑performance ASIC designs via UVM environments, debug complex RTL/testbench issues, and driving verification closure across IP, subsystem, and SoC levels in a fast‑paced, collaborative setting.

