Senior Digital VLSI Design Engineer

Own synchronization strategies for high-speed, complex IPs delivered to SOC teams, providing technical authority across multi-clock domains. Create and enforce synthesis constraints and full-chip CDC/RDC methodologies, including rigorous constraints and waivers to prevent silicon defects. Partner with Architecture and Chip Lead teams to review testability and DFT/clocking/reset architectures early, identifying metastability or reset-glitch risks before RTL freeze, and mentor teams through automated sign-off flows.