Senior Digital VLSI Design Engineer

Broadcom
Colorado, United States
Workplace: OnsiteFull timeUSD 121,900 - 195,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Mentorship","Technical leadership","Collaboration","Driving automation","Problem identification"]

Own synchronization strategies for high-speed, complex IPs delivered to SOC teams, providing technical authority across multi-clock domains. Create and enforce synthesis constraints and full-chip CDC/RDC methodologies, including rigorous constraints and waivers to prevent silicon defects. Partner with Architecture and Chip Lead teams to review testability and DFT/clocking/reset architectures early, identifying metastability or reset-glitch risks before RTL freeze, and mentor teams through automated sign-off flows.

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FursaFursa
Broadcom
Broadcom
1 month ago

Senior Digital VLSI Design Engineer

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Last checked: 12 days agoStatus: Live

Job Summary

Own synchronization strategies for high-speed, complex IPs delivered to SOC teams, providing technical authority across multi-clock domains. Create and enforce synthesis constraints and full-chip CDC/RDC methodologies, including rigorous constraints and waivers to prevent silicon defects. Partner with Architecture and Chip Lead teams to review testability and DFT/clocking/reset architectures early, identifying metastability or reset-glitch risks before RTL freeze, and mentor teams through automated sign-off flows.
Location: Colorado, United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Define and enforce synchronization strategies across complex, multi-clock domains in advanced process nodes.
  • •Own the constraint creation process for synthesis and the full-chip CDC/RDC methodology, including establishing constraints and waivers to ensure zero-defect silicon.
  • •Collaborate with Architecture and Chip Lead teams to review testability and DFT design, clocking, and reset architectures early in the design cycle.
  • •Identify potential metastability or reset-glitch issues before RTL freeze and drive resolution through sign-off readiness.
  • •Mentor the broader design team on Synthesis, DFT, and CDC/RDC best practices and streamline sign-off via automated flows for multi-site teams.

Pay and Benefits

Salary: USD 121,900 - 195,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kEsppEapPaid HolidaysPaid Leave

Key Requirements

  • •BSEE required; MSEE or PhD preferred.
  • •8+ years of related experience.
  • •Master structural and functional verification of clock domain crossings using industry-standard tools.
  • •Experience with constraint creation for synthesis and full-chip CDC/RDC sign-off methodology.
  • •Experience with high-speed interfaces where asynchronous boundaries are critical (e.g., SerDes, LPDDR, DDR, HBM).
Experience:8+ years
Education:Bachelor's
Skills:MentorshipTechnical leadershipCollaborationDriving automationProblem identification
Tech Stack:SynthesisDFTClock Domain Crossing (CDC)Reset Domain Crossing (RDC)SpyGlass CDC/RDCSpyglass LintJasperGoldMeridianSerDesLPDDR5LPDDR6DDR4DDR5HBMRTL freeze

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn