SMTS, Design Engineer

Micron Technology
San Jose
Workplace: OnsiteFull timeUSD 176,000 - 347,000 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Technical leadership","Mentorship","Project management","Technical communication","Cross-functional collaboration"]

Serve as a Senior Member of Technical Staff (SMTS) design authority in Micron’s NVEG organization, driving architecture and implementation of high-speed datapath circuits for next-generation NAND flash. Own design, layout, and optimization of IO blocks targeting 10+Gbps performance and power efficiency, leading SI/PI analysis and feasibility studies. Guide multi-functional task forces through exploration to silicon validation, resolve SI/PI root causes, and mentor engineers.

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Micron Technology
Micron Technology
1 week ago

SMTS, Design Engineer

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Job Summary

Serve as a Senior Member of Technical Staff (SMTS) design authority in Micron’s NVEG organization, driving architecture and implementation of high-speed datapath circuits for next-generation NAND flash. Own design, layout, and optimization of IO blocks targeting 10+Gbps performance and power efficiency, leading SI/PI analysis and feasibility studies. Guide multi-functional task forces through exploration to silicon validation, resolve SI/PI root causes, and mentor engineers.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Design and verify sophisticated IO/datapath blocks (e.g., input receiver, serializer/deserializer, clock distribution, equalizer, ZQ calibration, ONFI training, wave pipelines) to meet aggressive performance targets.
  • •Evaluate circuit topology trade-offs across power, area, and speed; conduct layout reviews and optimize circuit performance and efficiency.
  • •Lead early-stage exploration of next-generation IO architectures using system-level modeling, timing budget development, and SI/PI analysis to establish feasibility boundaries.
  • •Define block interface specifications and negotiate technical trade-offs with integration, TD, and SIRD teams; align with Applications Engineering on feasibility and risk.
  • •Partner with Product Engineering to design silicon experiments, lead root-cause analysis, correlate measurements to models, and propose fixes to improve yield and close performance gaps.

Pay and Benefits

Salary: USD 176,000 - 347,000 annually
Perks:Health InsuranceDentalVisionPaid LeavePaid HolidaysParental Leave

Key Requirements

  • •B.S. or M.S. in Electrical Engineering (or related field) with 12+ years of relevant IC design experience, including multiple successful tape-outs of high-speed IO circuits.
  • •Demonstrated technical authority in high-speed IO circuit design with deep understanding of signal integrity, power integrity, and performance optimization across PVT corners.
  • •Track record of technical leadership driving architectural decisions and leading technical task forces across multi-functional teams.
  • •Experience with physical design flows, layout optimization, and parasitic extraction for performance-critical circuits.
  • •Strong system-level modeling and SI/PI expertise for multi-Gbps interfaces, including transmission line modeling, power delivery network design, and crosstalk mitigation.
Education:Master's in Electrical Engineering
Skills:Technical leadershipMentorshipProject managementTechnical communicationCross-functional collaboration
Tech Stack:System-level modelingTiming budgetSI/PI analysisTransmission line modelingPower delivery network designCrosstalk mitigationPVT cornersLayout optimizationParasitic extractionCMOS device physicsBSIM modelingONFI trainingWave pipelinesEqualizerZQ calibrationInput receiverSerializer/deserializerClock distributionDRAM interface

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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